Logic-level defects that escape manufacturing tests pose reliability risks in modern systems and require functional testing to identify their activation and propagation behaviors. However, effective functional testing is limited by the high cost of long-cycle fault simulations. To address this challenge, we propose a Spatio-Temporal Graph Convolutional Network framework to efficiently and accurately predict the Fault Impact Probability on the circuit's function cross-over multiple function cycles, enabling rapid quantitative assessment of functionally possible faults. Our method represents gate-level netlists as spatio-temporal graphs, capturing both structural connectivity and short-range signal-propagation dynamics. With dedicated spatial and temporal encoders, the proposed ST-GCN enables accurate prediction of multi-cycle circuit-level FIP. Experiments on ISCAS’89 benchmarks show that the approach reduces fault-simulation cost by over an order of magnitude while maintaining high accuracy (mean absolute error as low as 0.024 for 5-cycle predictions). The framework supports both testability-metric-based and simulation-based feature construction, enabling a tunable balance between efficiency and accuracy. A case study on test point selection further demonstrates that using predicted FIPs to guide observation-point placement improves the detectability of multi-cycle, hard-to-detect circuit-level faults. Overall, this work provides a scalable solution for circuit-level multi-cycle fault-impact assessment and can be readily integrated into functional test generation and other Electronic Design Automation workflows.

Positive and unlabeled (PU) learning is a fundamental task in many applications, which trains a binary classifier from only PU data. Existing PU learning methods typically assume that training and test distributions are identical. However, this assumption is often violated due to distribution shifts, and identifying shift types such as covariate and concept shifts is generally difficult. In this paper, we propose a distribution shift adaptation method for PU learning without assuming shift types by using a few PU data in the test distribution and PU data in the training distribution. Our method is based on the importance weighting, which learns the classifier in a principled manner by minimizing the importance-weighted training risk that approximates the test risk. Although existing methods require positive and negative data in both distributions for the importance weighting without assuming shift types, we theoretically show that it can be performed with only PU data in both distributions. Based on this finding, our neural network-based classifiers can be effectively trained by iterating the importance weight estimation and classifier learning. We show that our method outperforms various existing methods with seven real-world datasets.

Chiplet systems that stack heterogeneous dies via 2.5D/3D integration use JTAG-based test access ports (TAPs) to validate inter-die links and enable in-field diagnosis. However, these TAPs create a shared attack surface: penetrating a single die can potentially expose control of the entire stack. Current countermeasures involve embedding a complete cryptographic engine in each chiplet, which increases the area and locks the protocol at tape-out, leaving it susceptible to future unknown attacks. This paper proposes a Software-Defined Secure Island (SDSI) architecture that decouples security policies from hardwired logic while satisfying non-functional requirements. Each chiplet instantiates an ultra-lightweight Secure Island Controller (SIC) macro that performs only two XORs and two additions per handshake. Meanwhile, a centralized secure island runs heavyweight cryptography in firmware using the multi-round SASL-JTAG+ protocol. SDSI enables scalable, adaptable test access protection by decoupling security from hardware. An FPGA implementation shows that the SIC macro occupies 11% of the area of an AES- 128 core and 37% of a SHA256 core, yet it supports 256 - to 512-bit keys with negligible growth. A security analysis demonstrates immunity to replay attacks because the authentication data is refreshed with each session. All future upgrades, such as longer keys, stronger hashes, and additional rounds, are delivered via firmware, providing scalable, field-upgradable protection for heterogeneous chiplet systems.

Diffusion models are powerful generative models but often generate sensitive data that are unwanted by users, mainly because the unlabeled training data frequently contain such sensitive data. Since labeling all sensitive data in the large-scale unlabeled training data is impractical, we address this problem by using a small amount of labeled sensitive data. In this paper, we propose positive-unlabeled diffusion models, which prevent the generation of sensitive data using unlabeled and sensitive data. Our approach can approximate the evidence lower bound (ELBO) for normal (negative) data using only unlabeled and sensitive (positive) data. Therefore, even without labeled normal data, we can maximize the ELBO for normal data and minimize it for labeled sensitive data, ensuring the generation of only normal data. Through experiments across various datasets and settings, we demonstrated that our approach can prevent the generation of sensitive images without compromising image quality.

Maximizing the area under the receiver operating characteristic curve (AUC) is a standard approach to imbalanced binary classification tasks. Existing AUC maximization methods typically assume that training and test distributions are identical. However, this assumption is often violated due to a covariate shift, where the input distribution can vary but the conditional distribution of the class label given the input remains unchanged. The importance weighting is a common approach to the covariate shift, which minimizes the test risk with importance-weighted training data. However, it cannot maximize the AUC. In this paper, to achieve this, we theoretically derive two estimators of the test AUC risk under the covariate shift by using positive and unlabeled (PU) data in the training distribution and unlabeled data in the test distribution. Our first estimator is calculated from importance-weighted PU data in the training distribution, and the second one is calculated from importance-weighted positive data in the training distribution and unlabeled data in the test distribution. We train classifiers by minimizing a weighted sum of the two AUC risk estimators that approximates the test AUC risk. Unlike the existing importance weighting, our method does not require negative labels and class-priors. We show the effectiveness of our method with six real-world datasets.

This paper proposes a novel Test Point Insertion (TPI) strategy to enhance the testability for multi-cycle Built-In Self-Test (BIST) for logic circuits. The approach leverages Multivariate Temporal-Spatial Graph Convolutional Neural Networks (MTS-GCN) and Reinforcement Learning to identify optimal Test Points (TPs). The proposed TPI method treats the testability information of a logic circuit as time-series data and employs Multivariate Time-Series Graph Neural Networks (MTGNN) to capture the relationship between the circuit's structural (spatial information) attributes and the temporal variability of signal line testability across capture cycles. A subsequent Multi-Layer Perceptron (MLP) computes the metric for each signal line to pinpoint potential TPs based on the extracted temporal-spatial features. Experimental evaluation based on benchmark circuits confirms the efficacy of the proposed model, which is trained with Deep Q-Networks (DQN), in improving the fault detection for multi-cycle logic BIST.

Maximizing the area under the receiver operating characteristic curve (AUC) is a popular approach to imbalanced binary classification problems. Existing AUC maximization methods usually assume that training and test distributions are identical. However, this assumption is often violated in practice due to {\it a positive distribution shift}, where the negative-conditional density does not change but the positive-conditional density can vary. This shift often occurs in imbalanced classification since positive data are often more diverse and time-varying than negative data. To deal with this shift, we theoretically show that the AUC on the test distribution can be expressed by using the positive and marginal training densities and the marginal test density. Based on this result, we can maximize the AUC on the test distribution by using positive and unlabeled data in the training distribution and unlabeled data in the test distribution. The proposed method requires only positive labels in the training distribution as supervision. Moreover, the derived AUC has a simple form and thus is easy to implement. The effectiveness of the proposed method is shown with four real-world datasets.

Adversarial training (AT) is a promising method to improve the robustness against adversarial attacks. However, its performance is not still satisfactory in practice compared with standard training. To reveal the cause of the difficulty of AT, we analyze the smoothness of the loss function in AT, which determines the training performance. We reveal that nonsmoothness is caused by the constraint of adversarial attacks and depends on the type of constraint. Specifically, the$L_\infty$constraint can cause nonsmoothness more than the$L_2$constraint. In addition, we found an interesting property for AT: the flatter loss surface in theinput spacetends to have the less smooth adversarial loss surface in theparameter space. To confirm that the nonsmoothness causes the poor performance of AT, we theoretically and experimentally show that smooth adversarial loss by EntropySGD (EnSGD) improves the performance of AT.

We propose a meta-learning method to improve the anomaly detection performance on unseen target tasks that have only unlabeled data. Existing meta-learning methods for anomaly detection have shown remarkable performance but require labeled data in target tasks. Although they can treat unlabeled data as normal assuming anomalies in the unlabeled data are negligible, this assumption is often violated in practice. As a result, the methods have low performance. Our method meta-learns with related tasks that have labeled and unlabeled data such that the expected test anomaly detection performance is directly improved when the anomaly detector is adapted to given unlabeled data. Our method is based on autoencoders (AEs), which are widely used neural network-based anomaly detectors. We model anomalous attributes for each unlabeled instance in the reconstruction loss of the AE, which are used to prevent the anomalies from being reconstructed; they can remove the effect of the anomalies. We formulate adaptation to the unlabeled data as a learning problem of the last layer of the AE and the anomalous attributes. This formulation enables the optimum solution to be obtained with a closed-form alternate update formula, which is preferable to efficiently maximize the expected test anomaly detection performance. The effectiveness of our method is experimentally shown with four real-world datasets.

This paper proposes a new loss function for adversarial training. Since adversarial training has difficulties, e.g., necessity of high model capacity, focusing on important data points by weighting cross-entropy loss has attracted much attention. However, they are vulnerable to sophisticated attacks, e.g., Auto-Attack. This paper experimentally reveals that the cause of their vulnerability is their small margins between logits for the true label and the other labels. Since neural networks classify the data points based on the logits, logit margins should be large enough to avoid flipping the largest logit by the attacks. Importance-aware methods do not increase logit margins of important samples but decrease those of less-important samples compared with cross-entropy loss. To increase logit margins of important samples, we propose switching one-vs-the-rest loss (SOVR), which switches from cross-entropy to one-vs-the-rest loss for important samples that have small logit margins. We prove that one-vs-the-rest loss increases logit margins two times larger than the weighted cross-entropy loss for a simple problem. We experimentally confirm that SOVR increases logit margins of important samples unlike existing methods and achieves better robustness against Auto-Attack than importance-aware methods.

Under the functional safety standard ISO26262, automotive systems require testing in the field, such as the power-on self-test (POST) . Unlike the production test, the POST requires reducing the test application time to meet the indispensable test quality (e.g., >90% of latent fault metric) of ISO26262. This article proposes a test point insertion technique for multi-cycle power-on self-test to reduce the test application time under the indispensable test quality. The main difference to the existing test point insertion techniques is to solve the fault masking problem and the fault detection degradation problem under the multi-cycle test. We also present the method to identify a user-specified amount of test points that could achieve the most scan-in pattern reduction for attaining a target test coverage. The experimental results on ISCAS89 and ITC99 benchmarks show 24.4X pattern reduction on average to achieve 90% stuck-at fault coverage confirming the effectiveness of the proposed method.

The variational autoencoder (VAE) is a powerful latent variable model for unsupervised representation learning. However, it does not work well in case of insufficient data points. To improve the performance in such situations, the conditional VAE (CVAE) is widely used, which aims to share task-invariant knowledge with multiple tasks through the task-invariant latent variable. In the CVAE, the posterior of the latent variable given the data point and task is regularized by the task-invariant prior, which is modeled by the standard Gaussian distribution. Although this regularization encourages independence between the latent variable and task, the latent variable remains dependent on the task. To reduce this task-dependency, the previous work introduced an additional regularizer. However, its learned representation does not work well on the target tasks. In this study, we theoretically investigate why the CVAE cannot sufficiently reduce the task-dependency and show that the simple standard Gaussian prior is one of the causes. Based on this, we propose a theoretical optimal prior for reducing the task-dependency. In addition, we theoretically show that unlike the previous work, our learned representation works well on the target tasks. Experiments on various datasets show that our approach obtains better task-invariant representations, which improves the performances of various downstream applications such as density estimation and classification.

We propose a method for improving adversarial robustness by addition of a new bounded function just before softmax. Several studies hypothesize that small logits (inputs of softmax) by logit regularization contributes to adversarial robustness of deep learning. Following this hypothesis, we analyze norms of logit vectors at the optimal point under the assumption of universal approximation and explore new methods for constraining logits by addition of a bounded function before softmax. We theoretically and empirically reveal that small logits by addition of a common activation function, e.g., hyperbolic tangent, do not improve robustness since input vectors of the function (pre-logit vectors) can have large norms. From the theoretical findings, we develop the new bounded function. The addition of our function contributes to adversarial robustness because it makes logit and pre-logit vectors have small norms. Since our method only adds one activation function before softmax, it is easy to combine our method with adversarial training. Our experiments demonstrate that our method is comparable to logit regularization methods in terms of robustness against untargeted attacks without adversarial training. Furthermore, it is superior or comparable to logit regularization methods and a recent defense method (TRADES) when using adversarial training.

This study proposes an optimal installed capacity of Distributed Energy Resources (DERs) for a small remote island (Aguni-Island) is belongs to Okinawa Prefecture in Japan. Photovoltaic (PV), Wind Generator (WG), Battery Energy Storage System (BESS), and Fuel Cell (FC) are considered to be installed for optimal sizing. The simulation conducted in this study has been simplified to account seasonal load and weather variations. This simulations aims to minimize the fuel and total cost of the system as it resulted in a total cost, which is lower than it was before DERs to be implemented. In addition, carbon dioxide emissions from diesel generators have been reduced.

This paper presents the problem of optimizing the annual operation, equipment configuration and capacity in a smart city with renewable energy and Combined Cooling Heating and Power (CCHP). The effectiveness of this study is demonstrated by comparing the case where renewable energy and CCHP are introduced and the case where only electricity purchased from the electric utility is used.

The variational autoencoder (VAE) is a powerful generative model that can estimate the probability of a data point by using latent variables. In the VAE, the posterior of the latent variable given the data point is regularized by the prior of the latent variable using Kullback Leibler (KL) divergence. Although the standard Gaussian distribution is usually used for the prior, this simple prior incurs over-regularization. As a sophisticated prior, the aggregated posterior has been introduced, which is the expectation of the posterior over the data distribution. This prior is optimal for the VAE in terms of maximizing the training objective function. However, KL divergence with the aggregated posterior cannot be calculated in a closed form, which prevents us from using this optimal prior. With the proposed method, we introduce the density ratio trick to estimate this KL divergence without modeling the aggregated posterior explicitly. Since the density ratio trick does not work well in high dimensions, we rewrite this KL divergence that contains the high-dimensional density ratio into the sum of the analytically calculable term and the lowdimensional density ratio term, to which the density ratio trick is applied. Experiments on various datasets show that the VAE with this implicit optimal prior achieves high density estimation performance.

In this paper, we propose a built-in self-diagnosis (BISD) mechanism for delay faults induced by degradation. This mechanism solely generates expected signatures using slower clock on the fly and requires no memory for storing pre-computed expected signatures. In our experiment, the proposed BISD mechanism is applied to benchmark circuits. Area overhead and diagnostic resolution are evaluated.

This paper proposed the wind sensorless identification method for wind turbine using online parameter identification. In the proposed On-line parameter identification is used to identify the parameter kopt and improve the characteristics in optimal torque control that does not require wind speed information. The parameter identification is performed using the Recursive least squares method in the wind turbine using PMSG. Further, the identied optimal parameter kopt contributes to the detection of all parameter error of the wind turbine and characteristic change with aged deteriorations. The effectiveness of the proposed identification method was veried by simulations with using MATLAB / SIMULINK.

Multi-cycle Test applies more than one capture cycles during the capture operation which is a promising way to reduce the test volume of Logic-BIST (Logic Built-in Self-Test) based POST (Power-on Self-Test) for achieving high fault coverage. However, the randomness loss of the capture patterns due to the large number of capture cycles obstructs the further improvement of fault coverage and pattern reduction. In this paper, we propose a novel approach to control the capture patterns by modifying the captured values of scan Flip-Flops (FFs) during capture operation to enhance the test quality of the capture patterns. In the approach, we insert FF-Control circuits between the scan FFs and the combinational circuit to improve the randomness of the capture patterns by loading toggle vectors/pseudo-random vectors. The experimental results of ISCAS89 and ITC99 benchmarks validated the effectiveness of the proposed methods in fault coverage improvement and random pattern reduction for Logic-BIST.

To attain the requirement of ISO26262 standard, the POST for automotive MCU needs to achieve high Latent Fault (LF) metric (>90% for ASIL D) within limited test application time (TAT). In this paper, we propose a new DFT technique named Fault-Detection-Strengthened (FDS) method to enhance the effect of test pattern reduction of the multi-cycle test for shortening the TAT of POST, and develop an original in-house tool named FVP-TPI (Fault Vanishing Point-TPI) to implement the FDS method to automotive MCU. The evaluation results on a latest commercial automotive MCU (62M gates) confirm the effectiveness (test volume compaction) and the practicability (smaller hardware overhead, shorter period of DFT) of the method.

We propose a robust multivariate density estimator based on the variational autoencoder (VAE). The VAE is a powerful deep generative model, and used for multivariate density estimation. With the original VAE, the distribution of observed continuous variables is assumed to be a Gaussian, where its mean and variance are modeled by deep neural networks taking latent variables as their inputs. This distribution is called the decoder. However, the training of VAE often becomes unstable. One reason is that the decoder of VAE is sensitive to the error between the data point and its estimated mean when its estimated variance is almost zero. We solve this instability problem by making the decoder robust to the error using a Bayesian approach to the variance estimation: we set a prior for the variance of the Gaussian decoder, and marginalize it out analytically, which leads to proposing the Student-t VAE. Numerical experiments with various datasets show that training of the Student-t VAE is robust, and the Student-t VAE achieves high density estimation performance.

Recently, reconfigurable devices are gaining increased attention for the development of IoT, Automotive and AI system. A new type of fine-grained reconfigurable device named MRLD (Memory Based Reconfigurable Logic Device) has been proposed which is constructed by general SRAMs without any programmable interconnect resources. It should be a promising alternative to FPGA with the benefits of low production cost, low power and small delay. In this paper, we overview the architecture and the operation principle of MRLD. We also propose a test strategy and algorithms of pattern generation for the interconnect defects referred to stuck-at and bridge faults under MRLD. Experimental results confirmed the effectiveness of the proposed test method.

This study focuses on how the cumulative excess returns (CER) of corporate bonds in the Japanese market respond to simultaneous publications of current net earnings and management's net earnings forecast. The estimation results using a regression model generalizing the interaction of the current net earnings and management's net earnings forecast show that the CER of corporate bonds is influenced mutually by the two pieces of information. In particular, we confirmed that declining current net earnings and management net earnings forecasts will have the most negative impact on corporate bonds. These results reveal interesting facts about the mechanism by which financial information is reflected in prices in the corporate bond market as well as the excess source of the investment return in asset management practice.

BIST based field testing is a promising way to guarantee the functional safety of intelligent and autonomous systems. To improve the fault coverage with less random patterns for BIST, sequentially observing some flip-flops (FFs) during multi-cycle test is useful. In this paper, we propose the methodology for selecting the Fault-Detection-Strengthened FFs in multi-cycle test by evaluating the structure of a circuit. The experimental results of ITC99 benchmarks and a real Electronic Control Unit (ECU) circuit show the effectiveness of the proposed methods in fault coverage improvement and random pattern reduction.

Modern high performance, high density integrated circuits use a very large number of metal layers, necessitating the need to deal with the problem of resistive open defects. Resistive opens often manifest as and are modeled as small delay faults. Furthermore, in deep sub-micron technologies, it is known that the additional delay of a line with resistive open fault is not only a function of the resistant of the faulty line but it is also dependent on the signal transition(s) on its adjacent lines. In this paper, we propose an efficient simulation method to simulate small delay faults and we use this simulator to diagnose resistive open faults. The fault simulator developed by us simulates all delay faults for one signal line simultaneously. This information is then used to deduce the candidate faulty lines in two steps. Experimental results for ISCAS'89 benchmark circuits show that by using the method proposed by us the faulty lines can be identified correctly in most cases.

This paper presents diagnosis methods for bridging faults between a clock line and a gate signal line. Scan-based simulation methods are applied while assuming that only scan-based flush tests are used. In view of the fact that initial states play an important role, we consider two possible scenarios: 1) all flip-flops are assumed to be reset table, and 2) flip-flops are not reset table. In order to handle unknown states due to the non-reset table flip-flops, we introduce heuristic techniques. The effectiveness of the proposed methods are evaluated by the experimental results for benchmark circuits.

In this paper, we investigate the effects of delay faults on clock lines under launch-on-capture test strategy. In this fault model we assume that scan-in and scan-out operations, being relatively slow, can perform correctly even in the presence of a fault. However, a flip-flop may fail to capture a value at correct timing during system clock operation, thus requiring the use of launch-on-capture test strategy to detect such a fault. In the paper, we first show simulation results providing a relation between the duration of the delay and difficulty of detecting such faults in the launch-on-capture test. Next, we propose test generation methods to detect such clock delay faults, and show some experimental results to establish the effectiveness of our methods.

With shrinking of LSIs, the diversification of defective mode becomes a critical issue. As a result, test patterns for stuck-at faults and transition faults are insufficient to detect such defects. N-detection tests have been known as an effective way for achieving high defect coverage, but the large number of test pattern counts is the problem. In this paper, we propose metrics based on the fault excitation functions and the propagation path function to evaluate test patterns for transition faults. We also propose the method for selecting the test patterns from the N-detection test set. From the experimental results, we show that the set of selected test patterns can detect the larger number of faults than other test set with the same number of test patterns.

Shrinking timing margins for modern high speed digital circuits require a careful reconsideration of faults and fault models. In this paper, we discuss detection of transition faults in the presence of small clock delay faults. We first show that in the presence of a delay fault on a clock line some transition faults may fail to be detected. We propose a test generation method for detecting such faults (simultaneous presence of two faults) which consist of a gate transition fault and a clock delay fault assuming launch-on-capture test environment. The proposed test generation method employs a standard stuck-at ATPG tool. In our test generation methodology, the conditions for detecting a clock delay fault are converted into those for detecting a stuck-at fault, by adding some modeling logic during the ATPG process. Experimental results for benchmark circuits show the effectiveness of the proposed methods.

This paper addresses the problem of simultaneous presence of multiple faults consisting of clock delay and gate transitions faults. The conditions of detecting a target multiple fault are converted into those for detecting a single stuck-at fault by adding some logic during the ATPG process. Experimental results show the effectiveness of our method by achieving nearly 100% fault efficiency.

Under the open fault model with considering the effects of adjacent lines, the open fault excitation is depended on the tests. Therefore, the layout information is needed to generate a test for an open fault. However, it is not easy to extract accurate circuit parameters of a deep sub-micron LSI. We have already proposed an open fault model without using the accurate circuit parameters. In this paper, we propose a new class of the pair of tests for the open fault called Ordered Pair of Tests (OPT). OPT is generated based on the fault excitation function as a threshold function of the adjacent lines. Also we propose a method for generating OPTs from the given stuck-at fault test set. The proposed method generates OPTs using only information about adjacent lines of the target open fault. Experimental results show that the proposed method can generate the OPTs for the open faults with high fault coverage.

This paper presents a diagnostic test generation method for transition faults. As two consecutive vectors application mechanism, launch on capture test is considered. The proposed algorithm generates test vectors for given fault pairs using a stuck-at ATPG tool so that they are distinguished. If a given fault pair is indistinguishable, it is identified. Therefore the proposed algorithm provides a complete test generation regarding the distinguishability. The conditions for distinguishing a fault pair are carefully considered, and they are transformed into the conditions of the detection of a stuck-at fault, and some additional logic are inserted in a CUT for the test generation. Experimental results show that the proposed method can generate test vectors for distinguishing the fault pairs that are not distinguished by commercial tools, and also identify all the indistinguishable fault pairs.

Defects in the modern LSIs manufactured by the deep-submicron technologies are known to cause complex faulty phenomena. Testing by targeting only stuck-at or bridging faults is no longer sufficient. Yet, increasing defect coverage is even more important. A stuck-open fault model considers transistor level defects, many of which are not covered by a stuck-at fault model. Further, test vectors for stuck-open faults also have the ability to detect the defects modeled by delay faults. This paper presents test generation methods for stuck-open faults using stuck-at test vectors and stuck-at test generation tools. The resultant test vectors achieve high coverage of stuck open faults while maintaining the original stuck-at fault coverage, thus offering the benefit of potential better defect coverage. We consider two types of test application mechanisms, namely launch on capture test and enhanced scan test. The effectiveness of the proposed methods is established by experimental results for benchmark circuits.

Test generation methods for transistor shorts using logic test environment are proposed. The fault models used are strong shorts and weak shorts, introduced in our earlier work. Our methodology consists of fault simulation, test generation and test compaction using gate-level tools to detect transistor faults but without resorting to use of transistor-level tools.

Under the modern manufacturing technologies, the open defect is one of the significant issues to maintain the reliability of DSM circuits. However, the modeling and techniques for test and diagnosis for open faults have not been established yet. In this paper, we give an important clue for modeling an open fault with considering the affects of adjacent lines. Firstly, we use computer simulations to analyze the defective behaviors of a line with the open defect. From the simulation results, we propose a new open fault model that is excited depending on the logic values at the adjacent lines assigned by a test. Next, we propose a diagnosis method that uses the pass/fail information to deduce the candidate open fault. Finally, experimental results show that the proposed method is able to diagnose the open faults with good resolution. It takes about 6 minutes to diagnose the open fault on the large circuit (2M gates).

Substantial attention is being paid to the fault diagnosis problem in recent test literature. Yet, the compaction of test vectors for fault diagnosis is little explored. The compaction of diagnostic test vectors must take care of all fault pairs that need to be distinguished by a given test vector set. Clearly, the number of fault pairs is much larger than the number of faults thus making this problem very difficult and challenging. The key contributions of this paper are: 1) to use techniques for reducing the size of fault pairs to be considered at a time, 2) to use novel variants of the fault distinguishing table method for combinational circuits and reverse order restoration method for sequential circuits, and 3) to introduce heuristics to manage the space complexity of considering all fault pairs for large circuits. Finally, the experimental results for ISCAS benchmark circuits are presented to demonstrate the effectiveness of the proposed methods

For deep-sub micron technology based LSIs, conventional stuck-at fault model is no longer sufficient for fault test and diagnosis. This paper presents a method of fault diagnosis for transistor shorts in combinational and full-scan circuits under logic test environment. Description of a short requires a very large number of physical parameters, and hence it is difficult, if not impossible, to describe precisely the behavior of transistor shorts. Therefore, two types of transistor short models were defined and algorithms to address the diagnostic problem were developed. The novelty of the algorithms is that they use conventional stuck-at fault simulation methodologies to diagnose transistor level shorts. Experiments were conducted on benchmark circuits to demonstrate the effectiveness of the method

We describe a method of identifying a set of target crosstalk faults which may need to be tested in synchronous sequential circuits. Our method classifies the pairs of aggressor and victim lines, using topological and timing information, to deduce a set of target crosstalk faults. In this process, our method also identifies the false crosstalk faults that need not (and/or cannot) be tested in synchronous sequential circuits. Experimental results for ISCAS'89 and ITC'99 benchmark circuits show that the proposed method is CPU time efficient in obtaining the reduced lists of the target crosstalk faults. Also, the lists of the target crosstalk faults obtained by our method are substantially smaller than the sets of all possible combinations of faults.

Recently, manufacturing defects including opens in the interconnect layers have been increasing. Therefore, a failure analysis for open faults has become important in manufacturing. Moreover, the failure analysis for open faults under BIST environment is demanded. Since the quality of the failure analysis is engaged by the resolution of locating the fault, we propose the method for locating single open fault at a stem, based on only detecting/un-detecting information on tests. Our method deduces candidate faulty stems based on the number of detections for single stuck-at fault at each fan-out branches, by performing single stuck-at fault simulation with both detecting and un-detecting tests. To improve the ability of locating the fault, the method reduces the candidate faulty stems based on the number of detections for multiple stuck-at faults at fanout branches of the candidate faulty stem, by performing multiple stuck-at fault simulation with detecting tests.

We have proposed a method for identifying candidate single stuck-at faults based on the ambiguous test set (Takahashi et al., 2003). In this paper, we propose enhancing methods for diagnosing single/multiple stuck-at faults under BIST environment to reduce the number of candidate faults. The enhancing method uses the number of detections for candidate faults and the first detecting test to diagnose the candidate faults. Moreover, we propose an enhancing method for diagnosing multiple stuck-at faults by using test-pairs.

We propose a method of identifying a set of crosstalk induced delay faults which may need to be tested in synchronous sequential circuits. During the fault list generation 1) we take into account all clocking effects, and 2) infer layout information front the logic level description. With regard to layout constraints we introduce two methods, namely the distance based layout constraint and the cone based layout constraint. The lists of the target faults obtained by the proposed methods are substantially smaller than the sets of all possible combinations of faults.

With increasing chip interconnect distances, open-interconnect is becoming an important defect. The main challenge with open-interconnects stems from its non-deterministic real-life behavior In this work, we present an efficient diagnostic technique for multiple open-interconnects. The algorithm proceeds in two phases. During the first phase, potential solution sets are identified following a model-free incremental diagnosis methodology. Heuristics are devised to speed up this step and screen the solution space efficiently. In the second phase, a generalized fault simulation scheme enumerates all possible faulty behaviors for each solution from the first phase. We conduct experiments on combinational and full-scan sequential circuits with one, two and three open faults. The results are very encouraging.

In order to generate tests for path delay faults we propose an alternative method that does not generate a test for each path delay fault directly. The proposed method generates an n-propagation test-pair set by using an N/sub i/-detection test set for single stuck-at faults. The n-propagation test-pair set is a set of vector pairs which contains n distinct vector pairs for every transition fault at a checkpoint (primary inputs and fanout branches in a circuit are called check points). We do not target the path delay faults for test generation, instead, the n-propagation test-pair set is generated for the transition (both rising and falling) faults of check points in the circuit, and simulated to determine their effectiveness for singly testable path delay faults and robust path delay faults. Results of experiments on the ISCAS'85 benchmark circuits show that the n-propagation test-pair sets obtained by our method are very effective in testing path delay faults.

Diagnosing multiple stuck-at faults in combinational circuits using singleand multiple-fault simulation is proposed. The proposed method adds (removes) faults from a set of suspected faults depending on the result of multiple-fault simulation at a primary output agreeing (disagreeing) with the observed value. However, the faults that are added or removed from the set of suspected faults are determined using single-fault simulation. Diagnosis is carried out by repeated addition and removal of faults. The effectiveness of the diagnosis method is evaluated by experiments conducted on benchmark circuits and it is found to be substantially superior compared to the previous known solutions. The method proposed in this paper can be used as a powerful tool at the preprocessing stage of diagnosis in an electron-beam tester environment.

Describes two methods of diagnosing crosstalk-induced pulse faults in sequential circuits using crosstalk fault simulation. These methods compare with observed responses and simulated values at primary outputs to identify a set of suspected faults that are consistent with the observed responses. In these methods, if the simulated values agree with the observed responses, then the simulated fault is added to a set of suspected faults, otherwise the simulated fault is removed from the set of suspected faults. The diagnosis methods repeat the above process for each time frame to identify the suspected faults. The first method is a basic method which determines the suspected fault list by using the knowledge about the first and last failures of the test sequence. The second method uses state information and focuses on reducing the CPU time for diagnosing the faults. The CPU time is reduced by using stored state information to calculate the primary output values at the present time frame. Experimental results for ISCAS'89 benchmark circuits show that the number of suspected faults obtained by our methods is sufficiently small, and the second method is substantially faster than the first method.

This paper describes a method of identifying a set of crosstalk-induced delay faults which may need to be tested in synchronous sequential circuits. In this process, the false crosstalk-induced delay faults that need not (and/or can not) be tested in synchronous sequential circuits are also identify. Our method classifies the pairs of aggressor and victim lines, using topological information and timing information, to deduce a set of faults that need to be tested in a sequential circuit. Experimental results for ISCAS'89 benchmark circuits show that the lists of the target faults obtained by the proposed method are sufficiently smaller than the sets of all possible combinations of faults.

In this work, we call a set of a constant number of test patterns that have a fixed fault coverage for any size of a given ILA a fixed coverage fixed size test set (FixCoST). In this paper, we first show the existence of FixCoSTs, each test pattern of which is applied to the rows and columns of the array under test, as binary patterns that are repetitions of a few cell-input patterns. Such FixCoSTs can be applied in a BIST framework. Next, we devise a means and formulate measures to evaluate the individual repetitive test patterns of such a FixCoST and the FixCoST as a set. Then, we exploit the repetitive nature of the constituent test patterns of the FixCoSTs to develop a BIST-amenable method for generating FixCoSTs that apply all permutations of binary patterns to each cell of the ILA under test.

In this paper, we propose a method that uses an EB tester and multiple/single fault simulators to diagnose multiple stuck-at faults in combinational circuits. Based on the primary output values and selected internal line values which are calculated by multiple/single fault simulators, faults are added to or removed from a set of suspected faults. The proposed method repeats additions and removals of faults to avoid missing actual faults in a faulty circuit. In order to reduce the number of lines to be probed by the EB tester, the proposed method selects internal lines to be probed by using a backward path tracing procedure. The experimental results show that the proposed method achieves a small number of suspected faults by probing a small number of internal lines.

We present a technique for identifying redundant crosspoint faults in, sequential PLAs with fault-free hardware reset. This technique can find most redundant crosspoint faults efficiently. Experimental results show that about 7% of crosspoint faults are redundant on an average in the sequential PLAs synthesized by a commercial design tool SYNARIO for MCNC LGSynth89 finite-state machine benchmarks.

In this paper, we propose a new method that uses single and multiple fault simulations to diagnose multiple stuck-at faults in combinational circuits. On the assumption that all suspected faults are equally likely in the faulty circuit, multiple fault simulations are performed. Depending on whether or not a multiple fault simulation results in primary output values that agree with the observed values, faults are added to or removed from a set of suspected faults. Faults which are to be added to or removed from the set of suspected faults are determined using single fault simulation. Diagnosis is effected by repeated additions and removals of faults. The effectiveness of the method of diagnosis has been evaluated by experiments conducted on benchmark circuits. The proposed method achieves a small number of suspected faults by simple processing. Thus, the method will be useful as a preprocessing stage of diagnosis using the electron-beam tester.

In this paper, we propose a method of diagnosing gate delay faults using delay fault simulation. In the method, suspected faults are deduced by fault simulation and backward path-tracing using diagnostic test-pairs with observed faulty responses. Also, by fault simulation using diagnostic test-pairs with fault-free responses, non-existent faults are deduced, and they are removed from the set of suspected faults. Finally, we present experimental results on the ISCAS'85 benchmark circuits. The experimental results show that by simple processes of backward path-tracing and fault simulation, this method achieves reasonable diagnostic resolutions in a short time.

In this paper, we propose an electron beam tester (EB-tester) aided fault diagnosis for combinational and sequential circuits based on sensitized paths. For combinational circuits, we enhance the previous set of sensitizing input pairs and present EB-tester aided fault diagnosis. For sequential circuits, we introduce a measure for selecting internal lines to be probed and present EB-tester aided fault diagnosis. Experimental results of ISCAS'85 and ISCAS'89 benchmark circuits show the efficiency of the presented methods.

In this paper, we consider the design for testability of multipliers based on the modified Booth Algorithm. We introduce two basic array implementations of the multiplier and present a strategy to design for c-testability. Using the proposed strategy we present two designs. The first design, which requires two primary test inputs, is c-testable under the single stuck fault model (SSF) with 17 test vectors. Also under the cell fault model (CFM) we present a design derived from the second implementation. This design, which requires only one primary test input, is c-testable with 34 test vectors and each of its cells can be tested by exhaustively applying cell input patterns.

In this paper, we propose an algorithmic method for generating a test for marginal delays and gate delay faults, called an MD test. The time at which the MD test activates the latest transition at the primary output changes linearly with the size of the target delay. (1) The MD tests determine at a given clock rate (observation time) whether a circuit tender test is marginal chip or not. (2) The MD tests determine the maximum circuit clock speeds. (3) The MD test detects the target gate delay fault regardless of the size of the fault by comparing the latest transition time at the primary output of the fault-free circuit and that of the faulty circuit. In order to determine the detectable size of gate delay faults the proposed method introduces a new extended timed calculus which calculates both the latest transition time at the line in the fault-free circuit and the transition time at the same line affected by a gate delay fault of maximum fault size. We also demonstrate experimental results for gate delay faults on ISCAS benchmark circuits to show the performance of our method.

This paper presents a study on an intelligent vehicle that has the driver's subjective evaluation model. The subject's driving task is to follow the car in front of him (the first car) and to keep the headway distance between the two cars consistent. Using the ARMA model and fuzzy knowledge, the author created the subjective evaluation model that can predict the driver's subjective evaluation when performing this driving task. He realized that the subjective evaluation feedback control system is very useful for future vehicles.

In this paper, we present a test for small gate delay faults in combinational circuits, called a tenacious test and describe a method for generating tenacious tests. We consider a single gate delay fault in a circuit on the assumption of that each gate has some appropriate gate delay. First, we introduce a tenacious testfor a small gate delay fault on line L. The tenacious testcan propagate the effect of a small gate delay fault at line L to primary outputs by the delay effect. Next, we present a method for generating tenacious tests by using a timed seven-valued calculus with consideration of delay of each gate in a circuit under test. Finally, experimental results are demonstrated for gate delay faults on ISCAS'85 benchmark circuits. Experimental results show that we can obtain tenacious tests for small gate delay faults with high fault coverage.

In this paper, we improve the previous method by enhancing a set of diagnostic tests and using an EB testing method. We first enhance the previous set of diagnostic tests to one of diagnostic tests consisting of the four sets, TP-1, TP-2, TP-3 and TP-4. We next present two diagnostic methods by using the enhanced diagnostic tests and an electron-beam tester (EB-tester). Experimental results show that the presented method identified fault locations within 0.2 to 5% of all stuck-at faults on all lines in the circuit by probing about 0.8 to 15% internal lines.