Computing on the smallest Internet of Things (IoT) devices is increasingly essential. Dedicated hardware solutions, while offering high efficiency and speed, often lack the programmability required to adapt to evolving algorithms. Small CPUs, similar in energy consumption, usually cannot match this performance but can be enhanced through meticulous programming in assembly language. Typically, this improvement comes at the cost of increased code size or necessitates switching to a more energy-consuming platform. In this paper, we propose a combined hardware/software approach to enhance the performance of data-intensive algorithms on modified, efficient, small-sized RISC-V CPUs. We demonstrate this method using the Number Theoretic Transform from the Kyber algorithm as a case study. Our approach resulted in a significant speed improvement, while maintaining a code size that is nearly the same and reasonable resource utilization increase.

The paper presents the design and measurements of a low noise integrated circuit in a CMOS 130 nm for the readout of a hybrid pixel detector operating in a single photon counting mode. A core of IC contains a matrix of$128\times256$square shaped pixels of$75~\mu \text{m}$pitch. Each readout pixel consists of a charge sensitive amplifier (CSA), a shaper, two discriminators, and two 14-bit counters. We present the novel CSA feedback circuitry with an effective resistance of 0.6$\text{G}\Omega $and sets of switches, which allows low noise operation and fast return to the CSA output baseline at the same time providing the possibility of operation with a higher flux of input pulses. The measured equivalent noise charge of IC (bump-bonded to silicon sensor) is only 44$\text{e}^{-}$rms at 15°C, the offset spread is 5.5$\text{e}^{-}$rms and the energy resolution is FWHM = 380 eV @ 8keV, which is currently the best result in single photon counting pixel detectors. The hybrid pixel detector can register up to 107 million photons/mm2 per second, while the power consumption per single pixel is about$42~\mu \text{W}$.

Semiconductor hybrid pixel detectors of X-ray radiation are recently commonly used in many fields, such as material science, medicine, and synchrotron measurements. One of the most common problems to be solved in the pixel detector design are offsets and gain spreads in the readout electronics, which come from very small sizes of the transistors used. The mentioned problem can be mitigated by implementing a “digital-assisted analog” design approach, where the offsets are corrected by trimming digital-to-analog converters (DACs), fed with proper digital data. To find the correct input value for each DAC, the execution of the calibrating procedure is necessary, which is usually run using assistive devices, such as PCs or FPGAs, and is a time-consuming task. This paper presents the concept of the pixel matrix detector on-chip calibration, that enables standalone improvement of the device accuracy. The proposed solution integrates the RISC-V-based microprocessor, Pixel Matrix Controller, and pixel matrix detector inside the single integrated circuit. The solution does not require data transfer out of the chip and is therefore significantly faster than off-chip methods.

An important development in digital X-ray imaging systems is a pulse amplitude measurement in each pixel in real-time. A single readout pixel usually has the dimensions of 100 µm × 100 µm or lower, and as it has to accommodate the analog front-end amplifier and digital back-end readout logic, the area available for an ADC is extremely low. Thus, in the design of the ADC the most emphasis has to be put on decreasing its silicon area. Also, as a single readout chip consists of thousands of pixels, the allowed power budget per pixel is in the order of tens of microwatts, hence the power consumption of the converter has to be kept very low as well. This paper describes a design and measurement results of two 4-bit flash ADC prototypes, fabricated in 180 nm and 40 nm processes, which fit into a single pixel and can be used in future X-ray imaging systems. To make the comparison more meaningful, both designs share exactly the same architecture, have identical resolution and sample rate. The architecture of the design, layout comparison and obtained test results are presented.

We report on the design of a prototype IC called FPDR90 dedicated for readout of hybrid pixel semiconductor detectors used for X-ray imaging applications. The FPDR90 has dimensions of 4 mm × 4 mm and was designed in CMOS 90 nm technology with 9 metal layers. The core of the IC is a matrix of 40×32 pixels with 100 μm ×100 μm pixel size. Each pixel contains a fast charge sensitive amplifier (CSA), a main amplifier stage, two discriminators and two 16-bit ripple counters. The data from pixel matrix are read out via a single LVDS output with 200 Mbps rate. Each pixel contains about 1800 transistors and has a static power consumption of 42 μW for nominal bias condition. The effective pulse shaping for nominal bias condition is 28 ns and the equivalent noise charge is only 106 e-rms (when the CSA connected to silicon pixel detector). In a high gain mode an average gain of the front-end electronics is 64 μV/e-. The effective offset spread (at the one sigma level) from pixel to pixel and with enabled trim DAC is only 0.76 mV (calculated to the CSA input it is only 12 e-rms). The maximum count rate per pixel depends on the effective CSA feedback resistance and the dead time in the front-end as low as 117 ns (paralyzable model) can be set. The FPDR90 can operate with two energy thresholds in the readout mode separate from exposure or in the continuous readout mode with both a single threshold.