In this paper, the performance of adaptive array antennas conformed to different faceted structures, namely, 2-faceted, 3-faceted, 4-faceted and 8-faceted structures, are studied and compared with each other in the context of adaptive beamforming. Faceted array antennas are chosen because they can achieve a wider scanning range compared to planar arrays. Each of the faceted arrays consists of eight circularly polarised antennas operating at 2.4 GHz. Beamforming is achieved according to two different optimisation criteria, which are the minimised mean square error (MMSE) and the maximised signal-to-interference-plus-noise ratio (MSINR). The adaptive algorithm, Least Mean Square (LMS), and the bio-inspired algorithm, Particle Swarm Optimisation (PSO), are used to calculate the complex excitations of the array elements in order to satisfy the optimisation criteria. The directivity of the 3-faceted array is high, 12.59 dBi, even when the desired signal is away from boresight. The results obtained suggest that the 3-faceted array is the most suitable for adaptive array applications compared to the other faceted structures.

This brief presents an efficient implementation of JPEG2000 encoding algorithm based on an architecture consisting of a coarse-grained dynamically reconfigurable instruction cell array and an embedded advanced RISC machine core. In this implementation, different tasks within the JPEG2000 encoding algorithm are allocated with proper computational resources to achieve high throughput. The proposed architecture is dynamically reconfigured for different tasks during the encoding process. Simulation results demonstrate that the proposed architecture provides a throughput of up to 52.1 f/s (or 19.18 ms/frame) to encode a 256 × 256 standard Lena test image. Compared with various digital signal processor & very long instruction word-based JPEG2000 solutions, the proposed architecture provides significant advantages in terms of throughput and energy consumption.

In this paper we propose a new algorithmic approach to achieve fault tolerance based on three dimensional cellular genetic algorithms (3D-cGAs). Herein, 3D architecture is targeted due to its amenability to implementation with current advanced custom silicon chip technology. The proposed approach is designed to exploit the inherent features of a cGA in which the genetic diversity is used as the key factor in identifying and isolating faulty individuals. A new migration schema is proposed as a mitigation technique. Several configurations concerning migration and selection intensity are considered. The approach is tested using four benchmark test functions and two real world problems which present different levels of difficulty. The overall results show that the proposed approach is able to cope with up to 40% soft errors (SEUs).

This paper aims to compare the effect of dynamically controlling the exploration-exploitation trade-off in cellular Genetic Algorithms (cGAs) from two perspectives: first, through lattice reconfiguration while dynamically changing the grid-neighbourhood ratio and thus taking advantage of their inherent structural properties; second, through local selection using a recently developed method known as anisotropic selection which allows to modify the overall population selection pressure at a local level. For both perspectives, the dynamic control of selection pressure is implemented constantly (every n generations) or adaptively based on the loss of diversity at the phenotype or the genotype space. Benchmark problems ranging from academic to real and combinatorial problems have been tackled in order to fairly compare both approaches. Statistical significance tests have also been carried out to support the results herein presented.

In this paper, we propose a parallel hybrid merge-select sorting approach for the implementation of K-best list sphere detection (LSD) multi-input multi-output (MIMO) decoder based on a recently developed novel Reconfigurable Instruction Cell Array (RICA). Several popular sorting algorithms adopted in MIMO decoding are analyzed and mapped onto our proposed platform. We discuss the targeted K-best LSD algorithm as well as the sorting scheme variations which have been tailored for our RICA architecture. Simulation results prove that our proposed hybrid sorting approach can significantly reduce the number of comparison and swap operations when selecting the K-best candidates. Our results show that a 50% speedup can be achieved compared to traditional single bubble sorting based K-best LSD MIMO decoder.

In this paper, we propose an implementation of a data encoder to reduce the switched capacitance on a system bus. Our technique focuses on transferring raw video data for multiple reference frames between off- and on-chip memories in an MPEG-4 AVC/H.264 encoder. This technique is based on entropy coding to minimize bus transition. Existing techniques exploit the correlation between neighboring pixels. In our proposed technique, we exploit pixel correlation between two consecutive frames. Our method achieves a 58% power saving compared to an unencoded bus when transferring pixels on a 32-b off-chip bus with a 15-pF capacitance per wire.

This paper investigates a distributed cellular Genetic Algorithm (dcGA) for the implementation of a GPS attitude determination system. Previously, a cellular GA architecture has been proposed considering several implementations; however, comparison among these reveals that accuracy is compromised when the population size is increased. In this paper, a distributed configuration approach is proposed and compared with previous implementations in the literature; a significant improvement in terms of accuracy is reported without increasing computational cost.

Multi-core architectures are increasingly being adopted in the design of emerging complex embedded systems. Key issues of designing such systems are on-chip interconnects, memory architecture, and task mapping and scheduling. This paper presents an integer linear programming formulation for the task mapping and scheduling problem. The technique incorporates profiling-driven loop level task partitioning, task transformations, functional pipelining, and memory architecture aware data mapping to reduce system execution time. Experiments are conducted to evaluate the technique by implementing a series of DSP applications on several multi-core architectures based on dynamically reconfigurable processor cores. The results demonstrate that the proposed technique is able to generate high-quality mappings of realistic applications on the target multi-core architecture, achieving up to 1.3times parallel efficiency by employing only two dynamically reconfigurable processor cores.

Wireless Internet-access technologies have significant market potential, particularly the Worldwide Interoperability for Microwave Access (WiMAX) protocol which can offer data rates of tens of megabits per second. A significant demand for embedded high-performance WiMAX solutions is forcing designers to seek single-chip multicore systems that offer competitive advantages in terms of all performance metrics, such as speed, power, and area. Through the provision of a degree of flexibility similar to that of a DSP and performance and power consumption advantages approaching that of an application-specific integrated circuit, emerging dynamically reconfigurable (DR) processors are proving to be strong candidates for processing cores in future high-performance multicore-processor systems. This paper presents several new single-chip multicore architectures for the WiMAX application based on recently emerging coarse-grained DR processor cores. A simulation platform is proposed in order to explore and implement various multicore solutions combining different memory architectures and task-partitioning schemes. This paper describes the different architectures, the simulation environment, and several task-partitioning methods and demonstrates that up to 7.3 and 12 times speedup can be achieved by employing eight and ten DR processor cores for both the WiMAX transmitter and receiver sections, respectively. A comparison with other WiMAX multicore solutions is given in order to demonstrate that our best solution delivers a high throughput at relatively low area cost.

This paper presents a method to reduce the computation and memory access for variable block size motion estimation (ME) using pixel truncation. Previous work has focused on implementing pixel truncation using a fixed-block-size (16 times 16 pixels) ME. However, pixel truncation fails to give satisfactory results for smaller block partitions. In this paper, we analyze the effect of truncating pixels for smaller block partitions and propose a method to improve the frame prediction. Our method is able to reduce the total computation and memory access compared to conventional full-search method without significantly degrading picture quality. With unique data arrangement, the proposed architectures are able to save up to 53% energy compared to the conventional full-search architecture. This makes such architectures attractive for H.264 application in future mobile devices.

This paper presents a cellular Genetic Algorithm (cGA) which aims at realizing a fault tolerant platform based on the inherent ability of cGAs to deal with Single Hard Errors (SHE) that could permanently affect the operation of a system. To attain this objective it is indispensable to control the parameters of the cGA which directly affect the efficiency and accuracy of its search process. Among the overall set of parameters, the migration rate and frequency, the grid size, and the shape and size of local neighbourhoods have a remarkable effect on the cGA performance. By appropriately controlling these parameters, the complex search space (presenting multi-peak fitness-function) associated with the practical case study of the investigation herein presented, is conveniently explored in terms of efficiency and efficacy. Initially, fitness score registers have been identified as critical for proper systempsilas operation. In case, SHEs occur at these registers, the algorithm will ignore possible good solutions and rapidly spread bad individuals. Experiments results show the faults effects regarding convergence time, search rate and results accuracy, as well as the cGA improvement on faulty scenarios when migration is applied following different selection and replacement criteria or increasing selection intensity through different local neighbourhoods configurations.

This paper presents a new approach to optimization of an energy-constrained modulation scheme for wireless sensor networks by taking advantage of a novel bio-inspired optimization algorithm. The algorithm is inspired by Wrightpsilas shifting balance theory (SBT) of evolution in population genetics. The total energy consumption of an energy-constrained modulation scheme is minimized by using the new SBT-based optimization algorithm. The results obtained by this new algorithm are compared with other popular optimization algorithms. Numerical experiments are performed to demonstrate that the SBT-based algorithm could be used as an efficient optimizer for solving the optimization problems arising from currently emerging energy-efficient wireless sensor networks.

Wireless internet access technologies such as WiMAX have significant market potential. The high demand for embedded high performance WiMAX solutions is forcing designers to seek multi-core systems which offer competitive advantages in terms of all performance metrics. By providing the flexibility of a DSP with performance and power consumption approaching that of an ASIC, emerging dynamically reconfigurable processors are proving to be stronger candidates than conventional general-purpose processors or DSPs for future multi-core systems. This paper presents several multi-core solutions, based on newly emerging dynamically reconfigurable processor cores targeting WiMAX based applications. Coming with a SystemC trace-driven multi-core simulator, a simulation platform has been proposed in order to explore and implement various multi-core solutions combining different task partitioning strategies and inter-process communication methods.

This work presents a novel reconfigurable Galois field multiplier embedded in a dynamically reconfigurable processor for real time programmable Reed Solomon (RS) encoder and decoder targeting various communication standards. The fundamental operation in Reed-Solomon encoding and decoding is the multiplication over Galois field (GF). The reconfigurable GF multiplier with single instruction multiple data (SIMD) support is presented here, as an instruction set extension to the processor. The processor supports the RS coding to be programmable for Galois Field (28) with its sixteen primitive polynomials and for all supported data block sizes. Various optimization techniques have been applied in order to enhance the processor throughput. The throughput achieved for RS (204,188) is up to 202 Mbps for the encoder demonstrating a future proof flexible design.

This paper presents a code compression and on-the-fly decompression scheme suitable for coarse-grain reconfigurable technologies. These systems pose further challenges by having an order of magnitude higher memory requirement due to much wider instruction words than typical VLIW/TTA architectures. Current compression schemes are evaluated. A highly efficient and novel dictionary-based lossless compression technique is implemented and compared against a previous implementation for a reconfigurable system. This paper looks at several conflicting design parameters, such as the compression ratio, silicon area, latency, and power consumption. Compression ratios in the range of 0.32 to 0.44 are recorded with the proposed scheme for a given set of test programs. With these test programs, a 60% overall silicon area saving is achieved, even after the decompressor hardware overhead is taken into account. The proposed technique may be applied to any architecture which exhibits common characteristics to the example reconfigurable architecture targeted in this paper.

The use of reconfigurable cores in system on chip (SoC) designs is increasingly becoming a trend. Such cores are being used for their flexibility, powerful functionality and low power consumption. Distributed arithmetic (DA) is a powerful algorithm widely used in many fields of multimedia for its efficiency. This paper presents a novel reconfigurable adder-based architecture for DA to realize the inner product which is the key computation in many digital signal processing applications. 1D DCT is mapped onto the architecture. Compared with some existing ASIC designs, the new architecture achieves good performance in area, speed and power.

This paper presents a code compression and on-the-fly decompression scheme suitable for coarse-grain reconfigurable technologies. A novel unit-grouping dictionary based compression technique utilizing special control bits to increase the effective storage capacity of the dictionaries is implemented and compared against an existing suitable technique for an example reconfigurable system. Compressions ratios in the range of 40%-59% are recorded with new scheme.

This paper presents the porting of an RTOS Micro C/OS-II on a novel reconfigurable instruction cell based architecture which fills the gap between DSP, FPGA and ASIC with high performance, high flexibility and ANSI-C support. WiMAX physical layer program has been implemented on the target architecture with the RTOS support. A semaphore based synchronization scheme is used to improve the task independence. The research lays a foundation for further exploration of multithreading on multiple target architectures.

A new system-level approach is needed to incorporate reconfigurability in IP-inegration design flow, in order to speed up the designer's productivity. To incorporate reconfiguration aspects of IPs, a multiple-context representation of the different functionalities is used that will be mapped on the re-configurable block during different run-time periods. Co-simulation scenario is proposed as a part of a system-on-chip (SoC) design and modelling. SystemC-HDL co-simulation scenario provides a way of checking interoperability of a single designed HW module with the SystemC model. As a case study, novel reconfigurable FFT and Viterbi architectures are modelled in SystemC, and co-simulated in a C-based WiMAX system. Area and power consumption of main blocks in WiMAX are analysed.

This paper presents a new direct implementation of a popular RTOS with an associated application - the WiMAX physical layer - on reconfigurable computing architectures. A novel coarse-grained reconfigurable instruction cell based architecture is chosen as the target architecture. Firstly an RTOS - Micro C/OS-II - was ported to the target architecture, and then the WiMAX physical layer program was partitioned into multiple OS tasks which communicate with each other through the synchronization approaches provided by this RTOS. The WiMAX physical layer program has been also implemented on the ARM7TDMI processor. The results show that the performance of the target architecture is much better than the ARM7TDMI, and not limited by the bottleneck of memory latency.

This paper presents some of the results obtained by using a prototype algorithmic level design space exploration tool currently under development. The tool is based upon multi-objective evolutionary algorithms. The paper highlights the tool's benefits and discusses its current abilities in terms of its experimental applications.

Code compression has been applied to embedded systems to minimize the silicon area utilized for program memories, and lower the power consumption. More recently, it has become a necessity for multiple-issue architectures, such as VLIW and TTA, to permit a viable realization of these designs. In this paper, a code compression and decompression scheme suitable for newly emerging reconfigurable technologies is presented, which pose further challenges by having an order of magnitude higher memory requirement due to much wider instruction words than typical VLIW/TTA architectures. Two dictionary-based lossless compression schemes are implemented and compared for an example reconfigurable system. This paper looks at several conflicting design parameters, such as the compression ratio, silicon area and speed. Test programs for a 2D DCT, minimum error, wimax and H.264 have been evaluated with compression ratios in the range of 41% to 62% recorded with the best scheme.

This paper presents a method of low-power variable-block-size motion estimation using pixel truncation. Previous work focused on implementing pixel truncation using fixed-block-size motion estimation. However, pixel truncation fails to give satisfactory results for smaller block partitions. In this paper, we analyse the effect of truncating pixels for smaller block partitions and propose a method to improve the frame prediction. To further reduce power consumption, we adopt low-complexity matching criteria for the highly truncated bit. The low-complexity matching criteria can work together with pixel truncation to reduce computational complexity without significantly degrading picture quality.

Various instruction and transaction based power estimation techniques for processor and on-chip buses have been proposed in the past. In this paper, the authors propose a heterogeneous power model to estimate the power utilized by complete processor based reconfigurable system-on-chip (SoC) platform. The proposed model estimates the power consumed by the SoC platform using instruction-based model as well as transaction-based model. In addition the authors estimate the power consumed by various bus arbitration policies used in the on-chip communication

Recently, double binary circular turbo code has received tremendous attention. Due to its better error-correcting capability than classical turbo code, it has commenced practical applications in current communication standards, such as DVB-RSC and IEEE 802.16 (Wimax). However current decoding schemes will incur a huge computation complexity. In this paper, authors present a novel decoding scheme for double binary circular turbo codes, which will not only reduce the computation complexity, but also give at least 0.5 dB performance gain compared with current decoding schemes

There is a high demand for low power and efficient implementation of complex arithmetic operations in many Digital Signal Processing (DSP) algorithms. The CORDIC algorithm is suitable to be implemented in DSP systems since its calculation for complex arithmetic is simple and elegant. However, the large number of iterations involved in CORDIC operation limits its speed performance seriously and also consumes large power. This paper presents three CORDIC IP cores which were implemented using a new CORDIC algorithm. Each of them has one of more distinctive performance in terms of power, area, speed and flexibility due to their different architectures.

Generic reconfigurable finite state machine (FSM) array architecture is presented in this paper. The architecture has been customized for reconfiguration targeting applications requiring large number of states with the added advantage of low power consumption. Examples of up to 256 states have been targeted in this paper. Compared with commercial FPGA devices, the architecture provides the following reductions: up to 89.3% in power consumption, up to 55.2% in area and around 8% in delay time

This paper presents a novel architecture for tap-length optimisation of the linear LMS equaliser. No analysis has previously been carried out to determine any tradeoff that exists in circuit area against power saving achieved. A low-complexity length update algorithm is employed to dynamically adjust and optimise the number of taps in the linear equaliser according to channel conditions. The results show that the chosen algorithm presents minimal overhead and reduces power consumed due to optimisation of the equaliser length. This paper presents the first complete architectural VLSI implementation of the length optimised equaliser and includes a performance study in terms of area and power

This paper presents an analysis of the vertical Bell Laboratories layered space time (VBLAST) receiver used in a multiple-input multiple-output (MIMO) wireless system from the hardware implementation perspective and identifies those processing elements that consume more area and power due to complex signal processing. This paper models a scalable VBLAST receiver based on minimum mean square error (MMSE) nulling criteria assuming a block flat fading channel. After identifying the major area and power consuming blocks, this paper proposes two area and power efficient VLSI architectures for the block that computes pseudoinverse of the channel matrix. This paper discusses different tradeoff issues in both architectures and compares them with the architectures in the literature

This paper presents a solution based on parallel-pipelined architectures for high throughput and power efficient FFT IP cores. Low power consumption can be gained through the combination of hybrid low power algorithms and architectures. A number of IP cores have been implemented for the comparison of the impact of parameterization on power/area/speed performance. The results show that up to 55% and 52% power saving can be achieved by the combination of the above techniques for 64-point 4-parallel-pipelined FFT and 16-point 2-parallel-pipelined FFT respectively, as compared to R4SDC pipelined FFTs.

The authors present a soft-input soft-output (SISO) turbo decoder based on the two-step soft-output Viterbi algorithm (SOVA). The turbo decoder has been implemented with the trace-back algorithm (TBA). It achieves power and area reduction by employing an additional transition metric unit (TMU) for the generation of reliability values, instead of using a FIFO block for retrieving the previously stored reliability values in the survivor memory unit (SMU). Simulation results are provided for bit error rate (BER) performance using constraint lengths of K=3, 4, and 5. Implementation results for K=5 are also provided showing 46% area and 15% power savings compared to a conventional SOVA decoder

This paper proposes two novel parallel-pipelined FFT architectures, based on multiplier-less implementation, targeting wireless communication applications, such as IEEE 802.11 wireless baseband chip and MC-CDMA receiver. The proposed parallel-pipelined architectures have the advantages of high throughput and high power efficiency. The multiplier-less architecture uses shift and addition operations to realize complex multiplications. By combining a new commutator architecture, and a low power butterfly with this approach, the resulting power and area savings are up to 31% and 20% respectively, for 64-point and 16-point FFTs, as compared to parallel-pipelined FFTs based on Booth coded Wallace tree multipliers.

The paper presents a new algorithm for low power implementation of digital filters. The algorithm reduces power consumption through a two phased strategy, which targets reducing the switched capacitance within the multiplier circuit. The first phase involves the segmentation of coefficients into more primitive components which could in turn be processed through a single shift and a more primitive multiplication operations. The second phase exploits the correlation among the new set of coefficients at the coefficient input of the multiplier for more reduction in switched capacitance. The paper describes the algorithm and its evaluation environment and provides results with a number of filter examples demonstrating up to 65% reduction in power compared to conventional filtering.

The paper proposes a hierarchical algorithm for low power implementation of digital filters. The algorithm processes data and coefficients in blocks of fixed sizes. During the manipulation of each block, coefficients are segmented into two primitive components. The accumulative effect of processing a sequence of blocks and segmentation results in up to 80% reduction in power consumption compared to conventional filtering. The paper describes the implementation of the hierarchical algorithm, its constituent components and the power evaluation environment developed. Results are provided which demonstrate the effectiveness of the algorithm.