This paper introduces a new method for designing power amplifiers (PAs) using a flexible, automatic approach. It employs a Gaussian process-assisted fast non-dominated sorting genetic algorithm (GP-NSGA-II) for both circuit synthesis and layout optimization. Traditional genetic algorithms are computationally intensive and have poor convergence, making them difficult to use with three-dimensional full-wave simulators. To address these issues, the authors incorporate Gaussian process regression from Bayesian optimization into NSGA-II, improving convergence and computational efficiency. The method integrates layout simulation and optimization, enabling automatic PA design with direct layout optimization. To demonstrate the method’s effectiveness, the authors design a wide-band PA and a tri-band PA using a 10-W gallium-nitride (GaN) high electron mobility transistor (HEMT). The tests show that the prototypes perform well: the wide-band PA has a power-added efficiency (PAE) of over 61% and an output power greater than 41.5 dBm in the 2-3 GHz band, while the tri-band PA achieves PAE values of over 59%, 55%, and 57% in the 0.7-1.1 GHz, 2.3-2.5 GHz, and 3.4-3.5 GHz bands, respectively, with output powers exceeding 41.2 dBm, 40.6 dBm, and 40.6 dBm.

In this article, a novel frequency-domain behavioral modeling approach for gallium-nitride (GaN) devices is presented. The proposed technique is based on using the canonical section-wise piecewise linear (CSWPL) model framework to interpolate the dc input and output bias voltages by a 2-D polynomial function. The basic theory associated with the developed model is described in detail and experimentally verified. The model is implemented in a commercial software and, then, validated through both dc and radio frequency (RF) tests with measured load-pull data from 6-W GaN devices. The achieved results demonstrate an excellent prediction capability, thereby proving the accuracy of the developed modeling methodology. Compared with the standard CSWPL model, the proposed model is able to predict the transistor behavior at different bias voltages with one single set of parameters, which greatly reduces the model complexity as well as the required extraction time. Compared with existing bias included models, the proposed solution shows accurate predictions over a wide range of input power levels and bias conditions, simultaneously. Additionally, the proposed model is utilized for a broadband power amplifier (PA) design for a further validation. The measurements carried out on the realized PA are compared with the simulations based on the proposed model. The comparison is performed at four different bias conditions. The agreement between measurements and simulations confirms the extracted model’s validity.