EDBT 2026 Demo / reviewers in the wild / expert
Warren D. Little
dblp:54/3553
· DBLP profile ↗
9ranked-venue papers
6as first author
0since 2021 · last 1982
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 8 · 5 first-authorGraphics, computer vision, multimedia, augmented reality and games · 1 · 1 first-authorHuman-computer interaction and ubiquitous computing · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
7 papers |
Integrated circuit design · 34% Parallel and multicore computing · 25% Performance modeling and evaluation · 21% | |
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 100% | |
| Computer graphics and multimedia
2 papers |
Rendering · 65% Geometric modeling and processing · 35% |
Topics — the 16 heaviest of 19, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Compilers and program optimization
dependence analysis |
0.0 | 1 | 1982 | Improved Time and Parallel Processor Bounds for Fortran-Like Loops · IEEE Trans. Computers 1982 |
Compilers and program optimization
parallelization |
0.0 | 1 | 1982 | Improved Time and Parallel Processor Bounds for Fortran-Like Loops · IEEE Trans. Computers 1982 |
Parallel and multicore computing › parallel scheduling
parallel loop scheduling |
0.0 | 1 | 1982 | Improved Time and Parallel Processor Bounds for Fortran-Like Loops · IEEE Trans. Computers 1982 |
Hardware accelerators and domain-specific architectures › machine learning accelerator › neural network accelerator › convolution acceleration
convolution accelerator |
0.0 | 1 | 1980 | Convolution Computer · IEEE Trans. Computers 1980 |
Geometric modeling and processing › computational geometry
polygon decomposition |
0.0 | 1 | 1979 | An Area Shading Graphics Display Systems · IEEE Trans. Computers 1979 |
Rendering
raster graphics |
0.0 | 1 | 1979 | An Area Shading Graphics Display Systems · IEEE Trans. Computers 1979 |
Rendering
display systems |
0.0 | 1 | 1976 | Enhanced graphics performance with user controlled segment files · SIGGRAPH 1976 |
Performance modeling and evaluation
simulation |
0.0 | 2 | 1973 | Serial Hybrid Computation and Errors in Hybrid Loops · IEEE Trans. Computers 1973 R68-30 Monte Carlo Solution of Partial Differential Equations Using a Hybrid Computer · IEEE Trans. Computers 1968 |
Integrated circuit design
analog and mixed-signal circuits |
0.0 | 3 | 1973 | Digital Multiplexing Analog Signals · IEEE Trans. Computers 1972 Serial Hybrid Computation and Errors in Hybrid Loops · IEEE Trans. Computers 1973 R68-30 Monte Carlo Solution of Partial Differential Equations Using a Hybrid Computer · IEEE Trans. Computers 1968 |
Integrated circuit design
asynchronous circuit design |
0.0 | 1 | 1975 | Asynchronous Arbiter Module · IEEE Trans. Computers 1975 |
Integrated circuit design
digital circuit design |
0.0 | 1 | 1974 | An Algorithm for High-Speed Digital Filters · IEEE Trans. Computers 1974 |
Integrated circuit design › digital signal processing circuits
digital filter |
0.0 | 1 | 1974 | An Algorithm for High-Speed Digital Filters · IEEE Trans. Computers 1974 |
Integrated circuit design › analog and mixed-signal circuits › data converters
analog-to-digital converter |
0.0 | 1 | 1972 | Digital Multiplexing Analog Signals · IEEE Trans. Computers 1972 |
Performance modeling and evaluation › simulation › analog and hybrid computer simulation
hybrid simulation |
0.0 | 1 | 1973 | Serial Hybrid Computation and Errors in Hybrid Loops · IEEE Trans. Computers 1973 |
Parallel and multicore computing › parallel architecture
parallel processor |
0.0 | 1 | 1980 | Convolution Computer · IEEE Trans. Computers 1980 |
GPUs and heterogeneous computing › heterogeneous computing systems
hybrid computer |
0.0 | 2 | 1973 | Serial Hybrid Computation and Errors in Hybrid Loops · IEEE Trans. Computers 1973 R68-30 Monte Carlo Solution of Partial Differential Equations Using a Hybrid Computer · IEEE Trans. Computers 1968 |
Methods — techniques the papers use, named apart from their topics
static analysis · 0.0dynamic analysis · 0.0pipelining · 0.0discrete convolution · 0.0manual segment control · 0.0monte carlo method · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1982 | Improved Time and Parallel Processor Bounds for Fortran-Like LoopsabstractDynamic characteristics of program execution must be studied in order to calculate meaningful time and parallel processor bounds. The paper entitled "Time and Parallel Processor Bounds for Fortran-Like Loops" [1] studies only the static interaction between statements within a program to arrive at these bounds. Consequently, very loose bounds are obtained for certain programs. Improved estimates of time and processor bounds are provided for two of the example programs presented in the above-mentioned paper. These estimates are based on an expression of the relationship between operations which calculate values and operations which later use those values as operands. Richard W. Heuft, Warren D. Little |
IEEE Trans. Computers | 2 |
| 1980 | Convolution ComputerabstractA special purpose computer is described to evaluate the discrete convolution of two sequences of numbers. This computer abandons the traditional model of convolution as a series of inner products which, for input sequences of length n, requires n multipliers and (n − 1) adders to complete a convolution calculation in (2n − 1) time steps. Instead, it is shown that by reorganizing the algorithm, n interconnected processing units are able to evaluate a convolution in n time steps. Each processing unit consists of a multiplier, an adder, and the necessary buffers. In addition to providing increased throughput, the proposed organization results in a highly modular structure with a well defined interconnection pattern. Richard W. Heuft, Warren D. Little |
IEEE Trans. Computers | 2 |
| 1979 | An Area Shading Graphics Display SystemsabstractA computer graphics display system for rapidly shading areas on a raster scan screen is described. With the system, the host computer provides the display controller with the parameters of a set of component trapezoids which cover the area to be shaded. The paper gives an algorithm for use in the host to decompose an arbitrary polygon into component trapezoids and it describes a microcomputer based controller to shade the trapezoids. Warren D. Little, Richard W. Heuft |
IEEE Trans. Computers | 1 |
| 1976 | Enhanced graphics performance with user controlled segment filesabstractThis paper describes a simple idea for extending the use of display segment files in computer display systems. The extension is to provide manual control of segment files in a display terminal as well as program control from a host computer. The use of display segments local to the display makes it possible to speed up the rate at which pictures are displayed when the communications line to the host computer is slow or when the host machine is time-shared and heavily loaded. The manual control of segments are terminal functions that work for any program including old programs that knew nothing about display segments. Warren D. Little |
SIGGRAPH | 1 |
| 1975 | Asynchronous Arbiter ModuleabstractThe design and operation of a simple two-input arbiter module suitable for implementing n-input arbiter trees are given in this correspondence. R. C. Pearce, J. A. Field, Warren D. Little |
IEEE Trans. Computers | 3 |
| 1974 | An Algorithm for High-Speed Digital FiltersabstractThis paper describes an algorithm that is suitable for fast implementations of nonrecursive and recursive digital filters. High speed is realized at the expense of memory; however, the memory-speed tradeoff is flexible so that many hardware and software implementations are practical. When memory is not limited, the time required to compute a filter output value is independent of the order of the filter. Warren D. Little |
IEEE Trans. Computers | 1 |
| 1973 | Serial Hybrid Computation and Errors in Hybrid LoopsabstractThis paper considers the stability and errors associated with various combinations of hybrid simulation modes, sampling sequences, and compensating schemes. Warren D. Little |
IEEE Trans. Computers | 1 |
| 1972 | Digital Multiplexing Analog SignalsabstractA method is presented that combines the multiplexing and A/D function to eliminate analog multiplexing switches. Warren D. Little, A. C. Capel |
IEEE Trans. Computers | 1 |
| 1968 | R68-30 Monte Carlo Solution of Partial Differential Equations Using a Hybrid ComputerabstractThis paper describes work carried out by the author while working for his Ph.D. degree. The work was done at the University of Arizona, Tucson, under the supervision of Prof. G. Kron, using Arizona Statistical Repetitive analog Computer (ASTRAC II). The ultra-high speed of ASTRAC II permitted the author of obtain Monte Carlo solutions of partial differential equations at a much higher rate than previously reported and to continuously display these solutions. Warren D. Little |
IEEE Trans. Computers | 1 |