This paper describes an MPEG-2 encoder architecture based on a hard-wired LSI with a control MPU. All basic functions of MPEG-2 MP@ML video compression are integrated in the dedicated LSI. For the motion estimation, a horizontally subsampled, diamond search was employed as a simplified first search step. It can reduce operations to 20% of the full-search, with an estimated SNR degradation of only -0.1 dB. To help achieve a single-memory interface, a pair of 81 MHz, 16 Mb SDRAMs are used as a frame buffer and a code buffer. Data bandwidth between the SDRAMs and the LSI is kept to less than 94% of the maximum data rate. Jobs assigned to the control MPU need be executed less frequently than those of the macroblock coding, which helps reduce the requirements for MPU performance to about 7 MIPS.

A VLSI chip set capable of real-time MPEG (Moving Picture Experts Group) video encoding/decoding has been developed. It is composed of an inter-frame prediction chip, a transform and quantization chip, and a variable length coding chip. To make the chip set more cost effective, the MPEG algorithms are first partitioned into three blocks on the basis of their characteristics. Individual chip architectures are designed with the use of programmable DSP and application specific array approaches. A hierarchical data transmission method is introduced for use among the chips and frame memories. By using three chips, an MPEG video encounter can compress a 30-frames/s image sequence of 352 pels*240 lines. A decoder can be constructed with two chips for the same sequence.>

A programmable real-time high-definition television (HDTV) signal processor (HD-VSP) has been developed. For conventional TV signals, a previously reported video signal processor (VSP) has introduced flexible software control capability based on subregional processing. In order to expand such flexibility for real-time HDTV signal processing, the HD-VSP employs eight VSP clusters and programmable time-expansion/compression units. An input HDTV signal is converted to eight time-expanded subregional signals to reduce their sampling rate to that of conventional TV signals. The converted signals are then processed by the eight clusters in the same manner as the VSP. Therefore, programs developed for conventional TV signals can be applied to HDTV with little modification. Processed signals obtained from the eight clusters are time-compressed and multiplexed to reconstruct an output HDTV signal. This HD-VSP has 16 component processors per cluster and is capable of 2.5 giga-operations/s. Several coder programs, including a discrete cosine transform coder and an intraframe differential pulse code modulation (PCM) coder, are developed to evaluate HDTV coding efficiency.>

The architecture is an expanded version of a previously reported video signal processor in which a number of parallel processor clusters can be combined in a tandem connection form or in a parallel connection form. The new video signal processor introduces programmable time-expansion and time-compression circuits to A-to-D and D-to-A converters, respectively, for coping with high speed HDTV signals. It also employs input/output switch units before and after parallel processor clusters. The introduction of input/output switch units to the parallel processor clusters makes it possible to input several video signals simultaneously. By these additional units, a HDTV signal is converted to a set of NTSC level video signals in the time-expansion circuit. Every NTSC level video signal is then delivered to parallel processor clusters through an input switch unit. After processing in clusters, NTSC level signals are converted to a HDTV signal through an output switch unit and time-compression circuits. This architecture can be applied to stereo scope processing. >

A single-board 14.3-MOPS (million operations per second) video signal processor module (VSPM) has been developed. The module is fully microprogrammable and processes up to a 128 pel*128 pel subimage every 16.7 ms. Using a number of homogeneous VSPMs aligned in parallel, a real-time video signal processing environment is provided on the basis of an overlap-save or overlap-add technique. An experimental system has been constructed in order to demonstrate the signal processor approach's effectiveness for video signals by implementing picture coding algorithms. Due to software control capability, various kinds of picture coding techniques can be evaluated by the system.>

Two important functional LSIs for the realtime Video Signal Processor (VSP) have been developed. One is the Pipelined Arithmetic Unit (PAU) and the other is the Address Generation Unit (AGU). The PAU chip employs a flexible pipelined architecture optimized for L1 or L2-norm distance calculation, used in a wide variety of image processing. The AGU chip, including 15-word register file for pointer alteration, offers a user-friendly two dimensional pointer addressing. A realtime Video Signal Processor Module (VSPM), composed of one PAU, four AGUs and memories, has been implemented for multiprocessor VSP configuration. Thanks to software control capability, various kinds of picture coding techniques can be evaluated by the system.

A real-time video signal processor (VSP), suitable for VLSI implementation, is proposed. In order to obtain software controllability for video signal processing in a real-time environment, the VSP employs a multiprocessor configuration, where a plural number of video signal processing modules (VSPMs) are connected to input, output and feedback buses. Each VSPM processes its own assigned sub-images without communicating from/to other VSPMs. As the VSP needs no overhead for VSPM communication, the number of VSPMs involved does not affect the VSP system performance. The homogeneous processor based approach, employed in VSP, will become the most suitable LSI implementation methodology in the near future, due to processor module regularity and system flexibility.