For ultra low power application, digital sub-threshold logic design has been explored. Extremely low power supply (VDD) of sub-threshold logic results in significant power reduction. However, it is difficult to convert signals from core logic to input/output (I/O) circuits since core VDD is vastly different from high I/O supply voltage. In this work, we propose a level converter based on dynamic logic style for sub-threshold I/O part, having a large dynamic range of conversion. For the level converter, high voltage clock signal needs to be delivered through separate clock path from core logic, leading to clock synchronization problem between high voltage and low voltage clocks. To overcome this issue, we employed a Clock Synchronizer. A test chip is fabricated in 130-nm CMOS technology in order to verify the proposed technique. Hardware measurement results show that the level converter successfully converts 0.3 V 8 MHz pulse to 2.5 V signal.

Performance variability in digital integrated circuits can largely affect parametric yield and product reliability in ultra deep submicrometer technologies. As a result, variation resilience is becoming an essential design requirement for future technology nodes, especially for timing critical applications. This paper proposes an on-chip variability sensor using phase-locked loop (PLL) to detect process, supply voltage (VDD), and temperature variations (process, voltage, and temperature variation) or even temporal reliability degradation stemming from negative bias temperature instability. Our analysis shows that control voltage (Vcnt) of voltage-controlled oscillator in PLL can be used as a dynamic performance signature of an operating IC. Along with the proposed PLL-based sensor circuit, we also propose a variation-resilient system technique using adaptive body biasing (ABB). The PLLVcntsignal is efficiently transformed to an optimal body bias signal for various circuit blocks to avoid possible timing failures. Correspondingly, circuits can be designed with significantly relaxed timing constraint compared to conventional approaches, where a large amount of design resources can be wasted to take care of the worst-case situations. We demonstrated our approach on a test chip fabricated in IBM 130-nm CMOS technology. Measurement results show that the PLL-based sensor is cable of tracking various sources of circuit variations. Optimization analysis shows that 42% and 43% reduction in area and power can be obtained using our approach compared to the worst-case sizing. The proposed study refers to our previous study introduced in with major improvements in measurement results and analysis.

In this work, we propose a Schmitt Trigger (ST) based differential sensing SRAM bitcell that can operate at ultra-low supply voltage. The proposed Schmitt Trigger SRAM cell addresses the fundamental conflicting design requirement of read versus write operation of a conventional 6T cell. Schmitt Trigger operation gives better read-stability and as well as better writeability compared to the standard 6T cell. The proposed ST bitcell incorporates a built-in feedback mechanism, achieving process variation tolerance - a must for future nano-scaled technology nodes. Measurements on 10 test-chips fabricated in 130nm technology show that the proposed Schmitt Trigger bitcell gives 58% higher read Static Noise Margin (SNM), 2X higher writetrip-point and 120mV lower read Vmin compared to the conventional 6T cell. The ST SRAM array is operational at 150mV of supply voltage.

Negative bias temperature instability (NBTI) in MOSFETs is one of the major reliability challenges in nano-scale technology. This paper presents an efficient technique to characterize and estimate the lifetime circuit reliability under NBTI degradation. Unlike conventional approaches, where a representative fMAX (maximum operating frequency) measurement from timing critical circuitry is used, we propose to utilize the standby circuit leakage IDDQ as a metric to detect and characterize temporal NBTI degradation in digital circuits. Compared to the fMAX based approach, the proposed IDDQ based technique benefits from lower test cost and improved capability of estimating reliability of complex circuitries such as ALUs and SRAM arrays. We have derived an analytical expression for circuit IDDQ from the analytical PMOS Vt degradation model (ΔVt ∝ t1/6). The proposed model is verified with measurement data obtained from a test chip fabricated in 130nm technology. Furthermore, we examine the possible applications of our proposed IDDQ based NBTI characterization. We show that the temporal degradation in static noise margin (SNM) of SRAM array and fMAX of random logic circuits are highly correlated to the IDDQ measurement, and this relationship can be used to predict long term circuit reliability.

This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize on-chip phase locked loop (PLL) as a sensor to detect process, VDD, and temperature (PVT) variations or even temporal degradation stemming from negative bias temperature instability (NBTI). We will show that control voltage (Vcnt) of voltage controlled oscillator (VCO) in PLL can dynamically capture performance variations in circuit. By utilizing the Vcnt signal of PLL, we propose variation resilient circuit design using adaptive body bias (VR-ABB). Vcnt is used to generate an optimal body bias for various circuit blocks in order to avoid possible timing failures. Correspondingly, circuits can be designed with a significantly relaxed timing constraint compared to the conventional approaches, where a large amount of design resources can be wasted to take care of the worst case situations. We have demonstrated our approach using an 8 bit ripple carry adder (RCA) as an example circuit. Results show that even under extreme variations, reasonable parametric yield can be maintained while minimizing other design resources such as area and power.

We propose a new low-power SRAM using bit-line Charge Recycling (CR-SRAM) for the write operation. In the proposed write scheme, differential voltage swing of a bit-line is obtained by recycled charge from its adjacent bit-line capacitance. In order to improve the data retention capability of un-selected cells during write, the power supply lines of memory cells in one column are connected to each other and separated from the power lines of other columns. A test-chip is fabricated in 0.13μm CMOS and measurement results show 88% reduction in total power compared to the conventional SRAM (CON-SRAM) at VDD=1.5V and f=100MHz.

We propose a novel Schmitt Trigger (ST) based fully differential 10 transistor SRAM (Static Random Access Memory) bitcell suitable for sub-threshold operation. The proposed Schmitt trigger based bitcell achieves 1.56X higher read static noise margin (SNM) (VDD = 400mV) compared to the conventional 6T cell. The robust Schmitt trigger based memory cell exhibits built in process variation tolerance that gives tight SNM distribution across the process corners. It utilizes fully differential operation and hence does not require any architectural changes from the present 6T architecture. At iso-area and iso-read-failure probability the proposed memory bitcell operates at a lower (175mV) VDD with 18% reduction in leakage and 50% reduction in read/write power compared to the conventional 6T cell. Simulation results show that the proposed memory bitcell retains data at a supply voltage of 150mV. Functional SRAM with the proposed memory bitcell is demonstrated at 160mV in 0.13μm CMOS technology.

Increasing source voltage (Source-Biasing) is an efficient technique for reducing gate and sub-threshold leakage of SRAM arrays. However, due to process variation, a higher source voltage can significantly increase data flipping in standby mode (Hold Failures) resulting in faulty memories. This imposes serious concerns in reducing standby power with source-bias. In this paper, we analyze the effect of source bias on hold failures under both inter-die and intra-die variations. We propose a self-calibrating SRAM for aggressively reducing leakage while maintaining the hold failures under control.