NAND flash memory-based solid-state drives (SSDs) are increasingly being used in both consumer and enterprise storage markets, due to their superior performance over hard disk drives (HDDs) and continuous bit cost reductions. With multiple-level cell technology memory device is capable of trading off the performance and endurance with bit density. The more bits per cell there are, the longer latency and shorter lifetime. On the other hand, the performance of such SSDs is limited due to NAND flash access speed as well as the need of garbage collection. Recently, storage class memories (SCMs) like resistive RAM (ReRAM) and phase change RAM (PRAM) have been developed to fill the bandwidth gap between DRAM and NAND flash memory. SCMs are nonvolatile and byte addressable, which are much faster and durable than NAND flash. Therefore, with SCMs, the storage performance would be significantly improved. Hybrid SSDs are promising cost-efficient storage solutions. Various types of memories like single-level cell (SLC), multiple-level cell (MLC), triple-level cell (TLC) NAND flash memories, and SCMs create lots of opportunities for new system architectures and algorithms. In this paper, the architecture and algorithm design overview of three types of hybrid drives including MLC/TLC NAND flash hybrid, SCM/MLC NAND flash hybrid, and SCM/MLC/TLC NAND flash tri-hybrid are presented. From the evaluation results, hybrid drives demonstrate better performance, endurance, and power consumption, compared to the MLC NAND flash only SSD. Furthermore, the relationship between device reliability and performance of the SCM/NAND flash hybrid SSD has been understood at a system level. There is a tradeoff between acceptable bit error rate of SCM and NAND flash. In addition, the decoding latency of SCM affects the performance of hybrid SSD more than that of NAND flash.

Solid-state drives (SSDs) are rapidly replacing hard disk drives in enterprise data centers due to their higher throughput and reliability. However, the SSD's random write performance is limited by the NAND flash memories within the SSD, which require garbage collection (GC). To improve the write throughput, a logical block address (LBA) scrambler has been previously proposed. However, there are two issues associated with this solution. First, with the LBA scrambler, SSD throughput actually worsens for some types of workloads, such as prxy_0. Second, a large table size is needed. In this paper, the first problem is solved by a write order (WO)-based GC scheme. In order to choose the victim block, the parameters of valid page ratio, write order, and erase count of the NAND flash blocks are collectively considered according to a new formula. A key advantage of utilizing the relative write order of the blocks is that an internal timer is not needed to monitor the ages of the blocks. Second, a sector bundling scheme is proposed to reduce the table size of the LBA scrambler. Based on the experimental results, with the two proposals, SSD throughput is improved by 2.4 times, and the table size of the LBA scrambler is reduced by 45%.

There is an increasing demand for the solid-state drive (SSD) due to its high speed, low power, and high reliability. However, random write intensive workload is not good for the SSD performance due to the inherent characteristics of the NAND flash memory. As the garbage collection (GC) causes the bottleneck of the SSD write performance due to the page-copy overhead, a NAND flash aware system is proposed to improve the SSD performance with a scheme called logical block address (LBA) scrambler. In the proposed scheme, new data are actively written to the fragmented pages in the next erase block. As a result, the number of valid pages inside the block is reduced when the block is recycled. Considering that there are NAND flash blocks full of valid pages in the proposed scheme, a skipping full block round robin (SFB_RR) GC policy is proposed, showing 0%-58% performance improvement compared with the RR GC policy. Furthermore, certain valid pages in the SSD have obsolete data due to the logical address remapping of the LBA scrambler, which cannot be invalidated by the conventional TRIM command, thus a SWEEP command is introduced. With the SWEEP command, maximum 12% additional SSD performance gain is obtained. From the experimental results, 35%-394% performance improvement, 27%-56% energy consumption reduction, and 25%-55% endurance enhancement are achieved by the proposed LBA scrambler scheme + SFB_RR GC policy + SWEEP command support, compared with the conventional SSD.

A 3D through-silicon-via (TSV)-integrated hybrid ReRAM/multi-level-cell (MLC) NAND solid-state drive's (SSD's) architecture is proposed with NAND-like interface (I/F) and sector-access overwrite policy for ReRAM. Furthermore, intelligent data management algorithms are proposed to suppress data fragmentation and excess usage of MLC NAND. As a result, 11-times performance increase, 6.9-times endurance enhancement and 93% write energy reduction are achieved. Both ReRAM write and read latency should be less than 3 μs to obtain these improvements. The required endurance for ReRAM is 105.