Demo Data from EDBT 2026 / reviewers in the wild / expert
Moriyuki Takamura
dblp:54/3985
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 1994
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
High-performance computing · 61% Parallel and multicore computing · 15% Processor architecture and microarchitecture · 15% |
Topics — the 8 heaviest of 9, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
High-performance computing › scientific computing systems
computational fluid dynamics |
0.0 | 1 | 1994 | Development and achievement of NAL Numerical Wind Tunnel (NWT) for CFD computations · SC 1994 |
High-performance computing
distributed memory systems |
0.0 | 1 | 1994 | Development and achievement of NAL Numerical Wind Tunnel (NWT) for CFD computations · SC 1994 |
Parallel and multicore computing
parallel architecture |
0.0 | 1 | 1994 | Development and achievement of NAL Numerical Wind Tunnel (NWT) for CFD computations · SC 1994 |
High-performance computing
supercomputer architecture |
0.0 | 1 | 1994 | Architecture of the VPP500 parallel supercomputer · SC 1994 |
Processor architecture and microarchitecture
vector processor |
0.0 | 1 | 1994 | Architecture of the VPP500 parallel supercomputer · SC 1994 |
High-performance computing › supercomputer architecture
vector supercomputer |
0.0 | 1 | 1994 | Architecture of the VPP500 parallel supercomputer · SC 1994 |
Interconnection networks and networks-on-chip › switch architecture
crossbar switch |
0.0 | 1 | 1994 | Architecture of the VPP500 parallel supercomputer · SC 1994 |
Distributed systems › distributed system architecture
distributed multiprocessor system |
0.0 | 1 | 1994 | Architecture of the VPP500 parallel supercomputer · SC 1994 |
Methods — techniques the papers use, named apart from their topics
parallel computation model · 0.0fortran · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1994 | Development and achievement of NAL Numerical Wind Tunnel (NWT) for CFD computationsabstractNAL Numerical Wind Tunnel (NWT) is a distributed memory parallel computer developed through joint research and development of NAL and Fujitsu. It is based on the analysis of CFD codes developed in NAL. The target performance is more than 100 times faster than VP400. In this paper, the parallel computation model employed in the development of the NWT is described. The specification and feature of the NWT and the NWT Fortran are discussed. Finally, performance evaluations and some applications are presented. We find that the target performance is attained.> H. Miyoshi, Masahiro Fukuda, T. Iwamiya, M. Tuchiya, Masahiro Yoshida, Kazuomi Yamamoto, S. Ogawa, Y. Matsuo, Takashi Yamane 0002, Moriyuki Takamura, Shin Okada, Yoshinori Sakamoto, T. Kitamura, H. Hatama, M. Kishimoto |
SC | 12 |
| 1994 | Architecture of the VPP500 parallel supercomputerabstractThe VPP500 vector parallel processor is a highly parallel, distributed memory supercomputer that has a performance range of 6.4 to 355 gigaFLOPS and a main memory capacity from 1 to 222 gigabytes. The system scalably supports between 4 and 222 processors interconnected by a high-bandwidth crossbar network. Three key aspects of the VPP500, which are in sharp contrast to current massively parallel systems, characterize its architecture. First the building block is a 1.6 gigaFLOPS vector processor that is more than an order of magnitude faster than the processors used in massively parallel processors (MPP). This high uniprocessor performance reduces the dependence on parallelism. Second the distributed memory architecture and high-bandwidth crossbar network eliminate many of the bottlenecks found in MPP systems. These allow efficient utilization of hardware and have the effect of lessening the complexity of programming parallel computers. Third the system realizes high throughput by its capability to arbitrarily partition the processing elements for flexible multiprocessing.> Teruo Utsumi, Masayuki Ikeda, Moriyuki Takamura |
SC | 3 |