Path integration is essential for spatial navigation. Experimental studies have identified neural correlates for path integration, but exactly how the neural system accomplishes this computation remains unresolved. Here, we adopt recurrent neural networks (RNNs) trained to perform a path integration task to explore this issue. After training, we borrow neuroscience prior knowledge and methods to unfold the black box of the trained model, including: clarifying neuron types based on their receptive fields, dissecting information flows between neuron groups by pruning their connections, and analyzing internal dynamics of neuron groups using the attractor framework. Intriguingly, we uncover a hierarchical information processing pathway embedded in the RNN model, along which velocity information of an agent is first forwarded to band cells, band and grid cells then coordinate to carry out path integration, and finally grid cells output the agent location. Inspired by the RNN-based study, we construct a neural circuit model, in which band cells form one-dimensional (1D) continuous attractor neural networks (CANNs) and serve as upstream neurons to support downstream grid cells to carry out path integration in the 2D space. Our study challenges the conventional view of considering grid cells as the principal velocity integrator, and supports a neural circuit model with the hierarchy of band and grid cells.

Brains reorganise knowledge offline to improve future behaviour, with 'replay' involved in consolidating memories, abstracting patterns from experience, and simulating new scenarios. However, there are few models of how the brain might orchestrate these processes, and of when different types of replay might be useful. Here we propose a framework in which a meta-controller learns to coordinate offline learning of a lower-level agent or model in 'sleep' phases to maximise reward in an 'awake' phase. The meta-controller selects among several actions, such as learning from recent memories in a hippocampal store, abstracting patterns from memories into a 'world model', and learning from generated data. In addition, the meta-controller learns to estimate the value of each episode, enabling the prioritisation of past events in memory replay, or of new simulations in generative replay. Using image classification, maze solving, and relational inference tasks, we show that the meta-controller learns an adaptive curriculum for offline learning. This lays the groundwork for normative predictions about replay in a range of experimental neuroscience tasks.

Exploration is essential in reinforcement learning, particularly in environments where external rewards are sparse. Here we focus on exploration with intrinsic rewards, where the agent transiently augments the external rewards with self-generated intrinsic rewards. Although the study of intrinsic rewards has a long history, existing methods focus on composing the intrinsic reward based on measures of future prospects of states, ignoring the information contained in the retrospective structure of transition sequences. Here we argue that the agent can utilise retrospective information to generate explorative behaviour with structure-awareness, facilitating efficient exploration based on global instead of local information. We propose Successor-Predecessor Intrinsic Exploration (SPIE), an exploration algorithm based on a novel intrinsic reward combining prospective and retrospective information. We show that SPIE yields more efficient and ethologically plausible exploratory behaviour in environments with sparse rewards and bottleneck states than competing methods. We also implement SPIE in deep reinforcement learning agents, and show that the resulting agent achieves stronger empirical performance than existing methods on sparse-reward Atari games.

A key goal of unsupervised learning is to go beyond density estimation and sample generation to reveal the structure inherent within observed data. Such structure can be expressed in the pattern of interactions between explanatory latent variables captured through a probabilistic graphical model. Although the learning of structured graphical models has a long history, much recent work in unsupervised modelling has instead emphasised flexible deep-network-based generation, either transforming independent latent generators to model complex data or assuming that distinct observed variables are derived from different latent nodes. Here, we extend amortised variational inference to incorporate structured factors over multiple variables, able to capture the observation-induced posterior dependence between latents that results from “explaining away” and thus allow complex observations to depend on multiple nodes of a structured graph. We show that appropriately parametrised factors can be combined efficiently with variational message passing in rich graphical structures. We instantiate the framework in nonlinear Gaussian Process Factor Analysis, evaluating the structured recognition framework using synthetic data from known generative processes. We fit the GPFA model to high-dimensional neural spike data from the hippocampus of freely moving rodents, where the model successfully identifies latent signals that correlate with behavioural covariates.

Environmental information is required to stabilize estimates of head direction (HD) based on angular path integration. However, it is unclear how this happens in real-world (visually complex) environments. We present a computational model of how visual feedback can stabilize HD information in environments that contain multiple cues of varying stability and directional specificity. We show how combinations of feature-specific visual inputs can generate a stable unimodal landmark bearing signal, even in the presence of multiple cues and ambiguous directional specificity. This signal is associated with the retrosplenial HD signal (inherited from thalamic HD cells) and conveys feedback to the subcortical HD circuitry. The model predicts neurons with a unimodal encoding of the egocentric orientation of the array of landmarks, rather than any one particular landmark. The relationship between these abstract landmark bearing neurons and head direction cells is reminiscent of the relationship between place cells and grid cells. Their unimodal encoding is formed from visual inputs via a modified version of Oja's Subspace Algorithm. The rule allows the landmark bearing signal to disconnect from directionally unstable or ephemeral cues, incorporate newly added stable cues, support orientation across many different environments (high memory capacity), and is consistent with recent empirical findings on bidirectional HD firing reported in the retrosplenial cortex. Our account of visual feedback for HD stabilization provides a novel perspective on neural mechanisms of spatial navigation within richer sensory environments, and makes experimentally testable predictions.

Bfloat16 ("BF16") is a new floating-point format tailored specifically for high-performance processing of Neural Networks and will be supported by major CPU and GPU architectures as well as Neural Network accelerators. This paper proposes a possible implementation of a BF16 multiply-accumulation operation that relaxes several IEEE Floating-Point Standard features to afford low-cost hardware implementations. Specifically, subnorms are flushed to zero; only one non-standard rounding mode (Round-Odd) is supported; NaNs are not propagated; and IEEE exception flags are not provided. The paper shows that this approach achieves the same network-level accuracy as using IEEE single-precision arithmetic ("FP32") for less than half the datapath area cost and with greater throughput.

Constructing and maintaining useful representations of sensory experience is essential for reasoning about ones environment. High-level associative (topological) maps can be useful for efficient planning and are easily constructed from experience. Conversely, embedding new experiences within a metric structure allows them to be integrated with existing ones and novel associations to be implicitly inferred. Neurobiologically, the synaptic associations between hippocampal place cells and entorhinal grid cells are thought to represent associative and metric structures, respectively. Learning the place-grid cell associations can therefore be interpreted as learning a mapping between these two spaces. Here, we show how this map could be constructed by probabilistic message-passing through the hippocampal-entorhinal system, where messages are scheduled to reduce the propagation of redundant information. We propose that this offline inference corresponds to coordinated hippocampal-entorhinal replay during sharp wave ripples. Our results also suggest that the metric map will contain local distortions that reflect the inferred structure of the environment according to associative experience, explaining observed grid deformations.

This paper introduces a new datatype, the High-Precision Anchored (HPA) number, that allows reproducible accumulation of floating-point (FP) numbers in a programmer-selectable range. The new datatype has a larger significand and a smaller range than existing FP formats and has much better arithmetic and computational properties. In particular, it is associative, parallelizable, reproducible and correct. The paper also describes how HPA processing can be implemented as part of Arm's new Scalable Vector Extension (SVE) together with proposals for new instructions aimed specifically at the new datatype. For the modest ranges that will accommodate most problems, HPA processing is much faster than FP arithmetic: performance modelling shows 2-lane HPA accumulation of FP64 operands is 9.5 times faster on Arm's new vector architecture than double double accumulation and accelerates a recently published software algorithm for 3-lane reproducible FP summation by a factor of 5.6. This paper also discusses instruction-level optimizations for FP32 and FP16 summations that further increase HPA performance relative to FP64 accumulations.

This paper shows that the various computations underlying spatial cognition can be implemented using statistical inference in a single probabilistic model. Inference is implemented using a common set of 'lower-level' computations involving forward and backward inference over time. For example, to estimate where you are in a known environment, forward inference is used to optimally combine location estimates from path integration with those from sensory input. To decide which way to turn to reach a goal, forward inference is used to compute the likelihood of reaching that goal under each option. To work out which environment you are in, forward inference is used to compute the likelihood of sensory observations under the different hypotheses. For reaching sensory goals that require a chaining together of decisions, forward inference can be used to compute a state trajectory that will lead to that goal, and backward inference to refine the route and estimate control signals that produce the required trajectory. We propose that these computations are reflected in recent findings of pattern replay in the mammalian brain. Specifically, that theta sequences reflect decision making, theta flickering reflects model selection, and remote replay reflects route and motor planning. We also propose a mapping of the above computational processes onto lateral and medial entorhinal cortex and hippocampus.

This paper presents a number of new high-radix ripple-carry adder designs based on Ling's addition technique and a recently-published expansion thereof. The proposed adders all have one inverting CMOS cell per stage along the carry-in to carry-out critical path and, at 16-b word lengths, the fastest of them matches the speed of a 16-b prefix adder for only 63% of the area. These adders will be of use in VLSI circuits implementing modern wireless DSP algorithms and in Floating-Point Unit exponent logic, both of which typically use short word length arithmetic.

This paper presents the detailed design of the ARM VFP11 divide and square root synthesisable macrocell. The macrocell was designed using the minimum-redundancy radix-4 SRT digit recurrence algorithm, and this paper describes a novel acceleration technique employed to achieve the required processor clock frequency of up to 750 MHz in 90 nm CMOS. Logical effort theory is used to provide a delay analysis of the unit, which demonstrates the balanced nature of the two critical paths therein.

This paper demonstrates how IEEE 754 floating-point standard compliant rounding can be merged with carry-propagate addition in floating-point unit (FPU) designs by using a novel adaptation of the prefix adder. The paper considers add/subtract, multiply, and SRT divide operations and demonstrates that in every case a generic rounding architecture based on a prefix adder with a small amount of additional logic is sufficient to cover all the rounding modes. Critical path analysis shows that the proposed architecture is compatible with contemporary pipelined FPU design practice, while using significantly less logic

We consider the problem of recoding a number to minimize the number of nonzero digits in its representation, that is, to minimize the weight of the representation. A general sliding window scheme is described that extends minimal binary sliding window conversion to arbitrary radix and to encompass signed digit sets. This new conversion expresses a number of known recoding techniques as special cases. Proof that this scheme achieves minimal weight for a given digit set is provided and results concerning the theoretical average and worst-case weight are derived.

We introduce a method for extracting the core of a residue number system (RNS) number within the RNS, this affording a new method for scaling RNS numbers. Suppose an RNS comprises a set of coprime moduli, m/sub i/, with /spl Pi/m/sub i/=M. We describe a method for approximately scaling such an RNS number by a subset of the moduli, /spl Pi/m/sub j/=M/sub J//spl ap//spl radic/M, with the characteristic that all computations are performed using the original moduli and one other nonmaintained short wordlength modulus.

We describe a scalable unified architecture for Montgomery multiplication over either of the finite fields GF(p) and GF(2n). This architecture has the advantage of possessing a new redundant binary adder that supports carry-save additions under either of the Galois fields without the need for an external control signal to specify which field is to be used. Its main advantage over previously reported dual field multiplier is that a control signal which is broadcast to all cells to suppress carries under GF(2nis not needed. Consequently, larger multipliers can be synthesised whose pipelined speed is independent of the buffering required for the control signal.

This paper presents the design of parameterized fixed-point integer multiplication, squaring and fractional division units. The units are targeted at the Virtex-II family of FPGAs (field programmable gate arrays) from Xilinx and are based on the small 18X18-bit multiplier blocks. New partial product creation and summation techniques that exploit the low level primitives are used that achieve a 20% area and a 30% delay reduction for multiplication. A dedicated squaring component is presented that offers substantial area savings of up to 50%. The division component uses the multipliers for pre-scaling to reduce the delay and complexity of each minimally redundant radix-8 stage.

This paper presents results from the design of an LNS addition/subtraction function targeted for implementation on FPGA. A parallel look-up scheme is used to reduce the critical path of the function approximation to a single second order polynomial approximation while maintaining an acceptable amount of ROM to store the coefficients needed to calculate the logarithmic addition/subtraction function. The addition/subtraction function is designed to have better-than-floating-point accuracy, which enables a fair future comparison with floating-point. Area and delay reductions are achieved in comparison with previous designs.

This paper introduces PAPA: packed arithmetic on a prefix adder, a new approach to parallel prefix adder design that supports a wide variety of packed arithmetic computations, including packed add and subtract with saturation, packed rounded average, and packed absolute difference. The approach consists of altering the prefix adder cell logic equations to take advantage of a previously unused "don't care" state. The principle of logical effort is employed to assess the delay of the new adder architecture by establishing the extra effort needed to select and drive the appropriate carry signal to the requisite sum sub-word. This adder will find applications in video processors and other multimedia-orientated processor chips that implement packed arithmetic operations.

Previously we have proposed a simple zerotree coding algorithm called Listless Zerotree Coding (LZC) that has a significantly lower coding memory requirement than SPIHT. However, LZC performs the SPIHT-like recursive tree search that produces reconstructed images of uneven visual quality at low bit-rates. Therefore, in this paper we propose a new LZC algorithm called Tree-Pruning Listless Zerotree Coding (TPLZC) that performs a raster tree search for a better reconstructed image quality. Nevertheless, the zerotree relation is no longer embedded in the raster tree search, so additional buffer memory will be required to store the matrix-wide zerotree relations. TPLZC utilizes a simple tree-pruning method and a flag bit-map to construct and store the entire zerotree structure. As a result, TPLZC exhibits not only a low coding memory requirement but also a low coding complexity.

We present a model of the firing of place and head-direction cells in rat hippocampus. The model can predict the response of individual cells and populations to parametric manipulations of both geomet(cid:173) ric (e.g. O'Keefe & Burgess, 1996) and orientational (Fenton et aI., 2000a) cues, extending a previous geometric model (Hartley et al., 2000). It provides a functional description of how these cells' spatial responses are derived from the rat's environment and makes easily testable quantitative predictions. Consideration of the phenomenon of remapping (Muller & Kubie, 1987; Bostock et aI., 1991) indicates that the model may also be consistent with non(cid:173) parametric changes in firing, and provides constraints for its future development.

We present a computational model of the neural mechanisms in the pari(cid:173) etal and temporal lobes that support spatial navigation, recall of scenes and imagery of the products of recall. Long term representations are stored in the hippocampus, and are associated with local spatial and object-related features in the parahippocampal region. Viewer-centered representations are dynamically generated from long term memory in the parietal part of the model. The model thereby simulates recall and im(cid:173) agery of locations and objects in complex environments. After parietal damage, the model exhibits hemispatial neglect in mental imagery that rotates with the imagined perspective of the observer, as in the famous Milan Square experiment [1]. Our model makes novel predictions for the neural representations in the parahippocampal and parietal regions and for behavior in healthy volunteers and neuropsychological patients.

The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses "flagged prefix addition" to merge rounding with the significand addition. The floating-point adder is implemented in 0.5 /spl mu/m CMOS, measures 1.8 mm/sup 2/, has a 3-cycle latency and implements all rounding modes. A modified version of this floating-point adder can perform accumulation in 2-cycles with a small amount of extra hardware for use in a parallel processor node. This is achieved by feeding back the previous un-normalised but correctly rounded result together with the normalisation distance. A 2-cycle latency floating-point adder architecture with potentially the same cycle time that also employs flagged prefix addition is described. It also incorporates a fast prediction scheme for the true subtraction of significands with an exponent difference of 1, with one less adder.

Although many good video coding algorithms for low bit rates have been proposed, none of them place much emphasis on hardware implementation. Hardware implementations should utilize low complexity video coding algorithms and have small memory requirements because high memory requirements increase implementation costs. In this paper we propose a very low complexity and high regularity video coding algorithm that is suitable for hardware implementation. The proposed video coding algorithm uses the 3D wavelet transform coding and is based on 3D zerotree theory. The coding memory required by the proposed video coding algorithm is also dramatically reduced to minimize the implementation cost.

In this paper we propose a video coding algorithm which has a very low coding memory requirement. The coding memory reduction was achieved by using two bit maps instead of lists to indicate the significant coefficients and the descendant sets. The coding complexity is also significantly reduced by exploiting the 3D wavelet transform and 3D zerotree coding. The low memory requirement and low coding complexity make the proposed algorithm suitable for hardware implementation.

Beerel (1994) showed that semimodular asynchronous circuits are totally self-checking with respect to multiple output stuck-at faults that are nonexitory and nonsubstitutional. We show that, in circuits with atomic gate implementations, it is possible to ensure that all exitory multiple output stuck-at faults will cause the circuit to halt.

A model of how internal and external sensory information contribute to the firing of place cells in the rat hippocampus, and of how these cells contribute to the rat's spatial behavior, is tested on a miniature mobile robot. The experiments show that crude visual, odometric and short-range proximity information provided by sensors on the robot is sufficient to enable the formation of a robust spatial code within rectangular environments. They further show that the model of navigation can accurately return the robot to an unmarked goal location. Since the rat's perceptual systems are probably similarly crude, these results support our intuition that the model of hippocampal function is reasonable in not demanding too much of its inputs. The combined robotic and neuronal simulation can be used to make predictions regarding both electrophysiological and behavioral experiments. Finally, the model is applied to the neural basis of navigation in humans.

Presents a new parallel GaAs 32-bit adder based on a combination of the Han-Carlson (1987) and Kowalczuk (1991) parallel adders. GaAs is particularly sensitive to loading, so our aim was to reduce the wire lengths and the fanout of each gate. Our architecture achieves this by significantly reducing the number of cells in the carry tree while not significantly reducing its speed. The delay of the adder fabricated in 0.6 /spl mu/m MESFET GaAs technology was measured at 1.27 ns, with a power dissipation of 114 mW at 0.9 V. The area is 0.3 mm/sup 2/ with a maximum density of 8000 transistors/mm/sup 2/. The figure of merit is 0.21 /spl mu/W/MHz/spl middot/gate.

The paper presents related techniques for converting a residue number system (RNS) number to binary, with and without scaling, that use the core function. The techniques remove the difficulties associated with conversion procedures based on the Chinese remainder theorem and the mixed-radix conversion technique. Two new methods for extracting the core of an RNS number are also presented that employ a parity bit to eliminate ambiguity.

This paper presents a GaAs IEEE floating point standard single precision multiplier. A modified carry save array is used in conjunction with Booth's algorithm to reduce the partial product addition and interconnection. A special rounding technique called Trailing-1's Predictor is used to speed up the final addition and rounding. The combination of the fast arithmetic architecture and compact layout style achieves 4 ns multiplication time with 3.5 W power dissipation at 75/spl deg/C giving 14 mW/MHz. The area is 2.43 mm by 3.77 mm (excluding pads) and uses 28,000 transistors to give a density of 3056 transistors/mm/sup 2/ for 0.8-/spl mu/m GaAs technology.>

The paper presents an analysis of the number of partial remainder digits and divisor bits that must be examined in the SRT division algorithm. The number of examined digits is found to be the same for both signed digit and 2s complement partial remainder representations, and appears to increase as 3log/sub 2/r approximately, where r is the radix of the divider. In some cases, it proves advantageous to examine a fractional number of remainder digits by inspecting more positive than negative bits.>

A model of short-term memory for serially ordered lists of verbal stimuli is proposed as an implementation of the 'articulatory loop' thought to mediate this type of memory (Baddeley, 1986). The model predicts the presence of a repeatable time-varying 'context' signal coding the timing of items' presentation in addition to a store of phonological information and a process of serial rehearsal. Items are associated with context nodes and phonemes by Hebbian connections showing both short and long term plasticity. Items are activated by phonemic input during presentation and reactivated by context and phonemic feedback during output. Serial selection of items occurs via a winner-take-all interaction amongst items, with the winner subsequently receiving decaying inhibition. An approximate analysis of error probabilities due to Gaussian noise during output is presented. The model provides an explanatory account of the probability of error as a function of serial position, list length, word length, phonemic similarity, temporal grouping, item and list familiarity, and is proposed as the starting point for a model of rehearsal and vocabulary acquisition.

A constructive algorithm is presented which combines the architecture of Cascade Correlation and the training of perceptron-like hidden units with the specific error-correcting roles of Upstart. Convergence to zero errors is proved for any consistent classification of real-valued pattern vectors. Addition of one extra element to each pattern allows hyper-spherical decision regions and enables convergence on real-valued inputs for existing constructive algorithms. Simulations demonstrate robust convergence and economical construction of hidden units in the benchmark "N-bit parity" and "twin spirals" problems.

A system for the classification of real 3D objects is presented. Ten objects are presented in arbitrary orientation (and position, within limits). The perception of an object is achieved by the use of multiple stereo pairs of images taken from different view positions. Classification of the spectrum of distances between edge-points perceived on an object is achieved using a constructive algorithm. Convergence to zero errors on the set of training examples is guaranteed. The generalization capability was tested on a set of 10 novel presentations of each object.>

The use of a constructive algorithm for pattern classification is examined. The algorithm, a ‘Perceptron Cascade’, has been shown to converge to zero errors whilst learning any consistent classification of real-valued pattern vectors (Burgess, 1992). Limiting network size and producing bounded decision regions are noted to be important for the generalization ability of a network. A scheme is suggested by which a result on generalization (Vapnik, 1992) may enable calculation of the optimal network size. A fast algorithm for principal component analysis (Sirat, 1991) is used to construct ‘hyper-boxes’ around each class of patterns to ensure bounded decision regions. Performance is compared with the Gaussian Maximum Likelihood procedure in three artificial problems simulating real pattern classification applications.

A system for the classification of real 3-D objects is presented. Ten objects are presented in arbitrary orientation (and position, within limits). The perception of an object is achieved by the use of multiple stereo pairs of images taken from different view positions. Classification of the spectrum of distances between edge-points perceived on an object is achieved using a constructive algorithm. Convergence to zero errors on the set of training examples is guaranteed. The generalization capability is tested on a set of 10–15 novel presentations of each object.