In recent years there has been a pronounced emphasis to develop alphanumeric display systems for document creation, filing, and text editing applications. This paper describes the design of a raster scan Display Processor which was specifically implemented to produce full page images ( 8½ in × 11 in or 11 in × 8½ in) which emulate typewriter output. A dual data path architecture is presented in which a Character Generator produces video images of text data, while a FAX Generator generates bit map video images corresponding to graphic forms used in the office. The design approach chosen provides degrees of functional richness that are not commonly present in current systems. Furthermore, the modular approach allows for a choice of whether or not to include forms overlay capability based on application requirements.

An approach is presented to analyzing and controlling hardware and software configurations of a time-sharing system given its load characteristics and desired performance. A mathematical model is developed which predicts response time to both interactive terminal requests and to compute bound programs. Estimates are obtained which relate performance to CPU load, file I/O load, and swap I/O load. Instrumentation contained within the UTS time-sharing system measures actual load and actual response during system operation, These measures suggest standards by which both load and response of time-shared systems could be compared, Extrapolation of the modeled and measured results allows prediction of performance for a variety of hardware configurations and user loads. Administrative controls allow dynamic tuning of the system during actual operation utilizing displays of current performance.

This paper focuses attention upon the design of a processor and memory system which is structured to achieve a satisfactory balance of processor speed and memory speed when both the processor and input–output controller are simultaneously competing for memory service. A mathematical model is developed to investigate the degree to which the processor is capable of overlapping memory references with instruction execution as a function of respective cycle times, the number of instruction "look-aheads," the number of independent memory modules, and input–output traffic. Utilizing this model, design trade-offs and performance indices are graphically examined for a hypothetical system.

This short note focuses attention upon techniques for dynamic memory allocation in multiprogrammed systems which employ the addressing mechanisms of paging and segmentation. Here, event indicators and mathematical tools are presented which supply characterizations of the paging and segmentation addressing processes. It is shown that these statistical characterizations form data bases which can be used to derive Bayesian storage allocation algorithms conditionally based upon usage, demand, and processing history. It is argued that these characterizations, and algorithms similar to those constructed here, provide a flexible basis for efficient memory management in multiprogrammed, and by extension, time-shared environments. Although emphasis is directed to managing primary (main) memory residence, the techniques could be extended to govern memory management for a hierarchy of storage devices.

A mathematical derivation of expected response time is presented for selected cyclic and priority scheduling disciplines, thereby demonstrating analytic techniques which may be utilized to evaluate such servicing doctrines. To illustrate the constant time quantum (round-robin) results, a hypothetical is defined and resolved.

This paper discusses some optimum design problems which arise when paging and segmentation are used in a multiprogrammed computer system, and suggests approaches to their solution. It is argued that design optimization depends fundamentally on the statistics of the typical software load presented to the computer system, and also that the investigation requires the aid of a total system model. Statistical techniques for defining software characteristics in such a model are presented. It is shown how these tools can be employed to simulate the changing contents of main memory; and as a further illustration, the simulation of an auxiliary memory is demonstrated. Graphs are given which show the variation of auxiliary memory performance with the number of associative cells available.