A voltage-controlled-oscillator(VCO)-based modulation PFM-PWM Buck converter is proposed to effectively reduce the output voltage ripple in PFM mode. The converter employs a VCO circuit instead of a hysteresis comparator to achieve PFM operation, ensuring a single inductor current pulse per cycle regardless of load current. A loop model for PFM mode is established for design of stability. Additionally, a hysteresis-based seamless mode transition method is incorporated to ensure converter consistent operating during full load range. Implemented using$0.18~\mu $m BCD technology, experimental results demonstrate minimal output voltage ripple of 2.5mV in PWM mode and of 8mV in PFM mode with empty load at output voltage of 5V. Moreover, the converter achieves optimal efficiency of up to 92%.

A novel adaptive peak inductor current limit for double hysteresis Buck working in DCM is proposed in this paper to improve efficiency at light load. Due to constant peak inductor current limit, conduction loss of double hysteresis Buck is the main reason that impose restrictions on efficiency at light load. To overcome the problem, peak inductor current limit decrease adaptively while the load changes from heavy to light by sampling time of sleep period. Furthermore, a dynamic quiescent current control method is adopted to reduce quiescent loss of double hysteresis Buck. The propose Buck chip is fabricated in$0.18 \mu\mathrm{m}$BCD process. The experiment results show that the maximum-improvement of efficiency is 3%.

A novel ladder control assisted startup for primary side regulated flyback converter without off-chip capacitors is proposed in this paper to reduce the overshoot voltage and optimize the startup time under different loads and input voltages. Large peak current in traditional soft-startup process may damage devices, and the detail reasons are illustrated in this work. To overcome the problems caused by the slow callback process of the error amplifier, sample information relative to the input voltage and load current is used by the ladder control circuit to generate a series of voltages to assist the startup. The proposed controller chip is fabricated in 0.18pm BCD process. The experiment results show that the overshoot voltage can be reduced from 20V to less than 0.3V and startup time can be reduced from 105ms to 42ms with the ladder control.

Type-IV dual-path step-down (T4 DPSD) converter is proposed with conversion efficiency improvement over wide input voltage. The proposed T4 DPSD converter adopts inductor and flying capacitor as power conversion elements, reducing power loss caused by large DCR in conventional Buck converter. Furthermore, the voltage stress of power devices and inductor current ripple are relieved. Thus switching loss and conductance loss are optimized simultaneously. Compared to previously proposed DPSD converters, the proposed T4 DPSD converter features negative voltage switching node. High-swing bootstrap (HSB) gate driver circuit with enhanced PSRR (Power Supply Rejection Ratio) is designed to charge bootstrap capacitor to adequate voltage, even if at lowest input voltage. Consequently, the full load efficiency at 5A is improved from 85% to 89.3%. And the peak conversion efficiency is 95.6% when input voltage is 2.7V to 4.2V with output voltage of 1.2V.

This paper presents a new design method based on neural network and co-simulation of MATLAB/Simulink and Virtuoso for solar energy harvesting system to power IoT applications. With the help of this new design method, a solar energy harvesting system with MPPT is designed and fabricated in 0.18 μm CMOS technology. The proposed MPPT scheme was able to track the maximum power point successfully with average tracking errors of 0.30% (pre-simulation) and 0.42% (test). And the efficiency is about 72.9%~76.8% when the light intensity is changing from 5000 lux to 11000 lux. In summary, the proposed new design method has the advantages of high accuracy, controllability and operability.

Variable on Time (VOT) control is proposed in the paper. Compared to conventional constant on time (COT) control, the on time of VOT control is modulated by output of error amplifier, rather than fixed voltage. VOT controlled buck converter shows significant duty cycle extension than COT control, especially for high switching frequency and wide input/output range applications, such as DVS converters. The duty cycle limitation of COT control is then broken through. The small signal model derivation based on Describing Function (DF) is given. A 1MHz 12V-1.2V buck converter with VOT control is designed with 0.35μm BCD process. Simulation results show that the recovery time is 5μs for 4A load step, and the undershoot voltage is decreased from 50mV to 35mV, by using VOT control. The voltage scaling speed is 20μs/V for 47μF output capacitor. The reference up-tracking shows FOM of 0.42s/(F·V), which is much better than previous works.

The canonical signed digit (CSD) coding is widely used in digital arithmetic operations due to its property that there is no adjacent nonzero digits in the encoded numbers. However, the benefits of the CSD coding may be faded because of the recursive conversion process from the binary representations. This paper presents a novel pseudo CSD coding method, which takes the merits of CSD, while simplifies the conventional conversion process. The simulation results indicate that the proposed converter can achieve at least 31.8% speed improvement and 42.9% energy reduction for a 16-bit binary operand at 1.2V in a 0.13-μm CMOS technology. It could run even faster than the competitors when the operand length increases.

Modern low-power system on a chip needs direct current converter with dynamic voltage scaling (DVS) ability for core power supply. The converter output should be accurate voltage across the full load current and voltage scaling range. An integrated buck converter for DVS application is proposed in this brief. Voltage mode phase lead compensation is implemented in the converter, with much smaller passive components than conventional type-III compensation. To improve accuracy, the output voltage error accompanied with load current and reference voltage caused by finite loop gain in analog control loop is corrected by the digital error corrector. The output voltage is compared by two comparators whose threshold voltage is about 10 mV above and below the reference voltage, respectively. The duty cycle is slightly adjusted by finite state machine according to outputs of the two comparators. Experimental results show that the converter is well regulated over an output range of 0.7-1.8 V, with step voltage of 25 mV. When load current suddenly changes between 170 and 500 mA, the overshoot and undershoot voltage are 32 and 50 mV, respectively. Load regulation is maintained about 1% throughout the full load range. The voltage error is within ±10 mV in the voltage scaling range.

An integrated synchronous buck converter with adaptive dead time controlled driver is presented in this paper. The integrated synchronous buck converter works in 2MHz PWM mode and the output voltage can be programmed by digital interface, which is suitable for powering the processor core and internal memory with dynamic voltage scaling (DVS) capability. The controller provides 0 and 100% duty cycles during DVS, maximizing tracking speed while saving power. The driver circuit detects body diode conduction by a proper biased N-type transistor. The synchronous N-type power MOS is turned on at the falling edge of body diode conduction detection in both DCM and CCM. The P-type power MOS is turned on at the falling edge of dead time detection in CCM. As a result, the dead time varies according to the load current, while the conduction time of the body diode in the synchronous power MOS is approaching to the delay of logic circuit and gate driver. The dead time control logic and gate driver are designed with low time lag to minimize body diode conduction time. Experimental results show that the converter can achieve fast reference tracking and the conversion efficiency is up to 90%.

A voltage mode power converter with the function of digitally duty cycle tuning is presented. Enough loop gain is required to guarantee a good load regulation. In the proposed design, the load regulation can be improved through digitally duty cycle tuning, based on phase lead compensated voltage mode power converters. The whole circuit is implemented in a 0.13μm 1P8M CMOS process. The simulation results show that the output voltage's deviation can be controlled within ±10mV when the load current steps from 200mA to 1.65A, and a 14μV/mA load regulation can be obtained.