Despite extensive research, the upconversion of 1/f noise into phase noise in harmonic oscillators is still an open topic of investigation. A few upconversion mechanisms are not fully understood yet. In particular, in class-B CMOS oscillators, the reason why a large tail capacitance combined with transistors entering the triode region for a portion of the oscillation cycle dramatically amplifies the 1/f noise upconversion has not been clearly pinpointed. This work introduces a simple yet powerful model to fully capture the 1/f noise upconversion mechanism. It shows that when the transistors enter the triode region, charge sharing between the tail capacitance and the tank capacitance injects a noise charge into the tank, generating phase noise perturbations quantified by the impulse sensitivity function. The analytical description results in closed-form equations that predict the$1/f^{3}$phase noise sideband accurately, without relying on complex harmonic analysis or specific device nonlinearities. The excellent agreement with simulations performed both using idealized and real 55nm CMOS transistor models confirms the validity and robustness of the proposed framework, offering new insights and practical design guidelines for low phase noise CMOS oscillators.

This article analyzes the behavior of a single supply asymmetric Doherty power amplifier, made of two switched-capacitor power amplifiers (SCPAs) and a power combining network. The proposed analysis shows that there is an optimal power partition between the two SCPAs that maximizes the efficiency at each output power level. The optimal control of the PA leads to two power back-off (PBO) efficiency peaks, whose magnitude depends on the size of the switches of each SCPA and on the matching network design. The optimization of both switch sizing and output network design is carried out analytically. The achieved theoretical results are then verified by transistor-level simulations. They have also been validated by measurements performed on a prototype, fully integrated in a commercial 22-nm CMOS technology, at an operation frequency of 2.3 GHz.

This paper presents a compensation and calibration technique for lumped-element Lange hybrid couplers. The target of the compensation is the reduction of the quadrature error introduced by lossy reactive components. An approximated, but reasonably accurate, analysis links the finite quality factor of the passive components to the quadrature error. A simple compensation technique, that corrects for the quadrature error, is proposed along with a calibration procedure. To verify the effectiveness of the proposed technique, a lumped-element Lange hybrid coupler working at an intermediate frequency of 3GHz is embedded in a fully integrated image-reject up/down-converter implemented in a 28nm bulk CMOS technology. Measurements show that the proposed technique yields an increase of the image rejection ratio from 24dB to 45dB for an up converted signal at 28GHz.

The design of switch drivers in reconfigurable switched capacitor dcdc converter is characterized by the need of several floating supplies to avoid exceeding the voltage ratings of the transistors used to implement the drivers. This work describes circuit solutions to tackle this issue without resorting to a wide set of large capacitors, favoring the integration of the converter.

This paper proposes a step-up DC-DC converter that regulates the output voltage in order to supply a micro-power digital processor, starting from a low-voltage input source such as a harvester. The converter is based on a reconfigurable Fibonacci and binary switched-capacitor architecture and is fully integrated in a CMOS technology with the exception of three flying capacitors. The circuit includes all the auxiliary blocks needed in order to self-configure the conversion ratio and to power the system up. According to detailed simulation results, the proposed circuit regulates to 1.2V an input voltage from 0.3V up to 0.6V, with an average efficiency of 83%.

We present a behavioral analysis of two different transceiver architectures for UWB breast cancer imaging employing a SFCW radar system. A mathematical model of the direct conversion and super heterodyne architectures together with a numerical breast phantom are developed. FDTD simulations data are used on the behavioral model to investigate the limits of both architectures from a circuit-level point of view. The result is that the simplicity of the direct conversion makes the receiver more robust toward the critical circuit impairments for this application, that is the random phase mismatches between the TX and RX local oscillators.

We present a study of tail-bias-current 1/f noise upconversion into 1/f3phase noise for both Colpitts and differential-pair LC oscillators. We focus on the Groszkowski effect, i.e. the shift in oscillation frequency induced by the higher current harmonics flowing into the LC tank of a harmonic oscillator. Quantitative results match very well numerical simulations run with spectreRF, and show that the Groszkowski effect may indeed be a dominant cause of 1/f3phase noise generation.

This paper presents a 2.2 GHz receiver front-end capable of an extreme current reuse, where the low-noise amplifier, the quadrature mixers and VCOs only draw 1.3 mA from a 1V supply. A careful time-variant analysis is carried out, resulting in a very accurate expression of the conversion gain and bandwidth of the downconverter. A prototype, implemented in a 90 nm CMOS technology, shows 27 dB gain over a 14 MHz bandwidth, with a noise figure of 13 dB. The input-referred 1 dB compression point is -23.7 dBm.

The increasing interest in impulse radio UWB communication links focuses the research interest on building blocks optimized for these specific systems. In this context, this paper proposes a ring oscillator for an impulse radio UWB transmitter. A multiloop ring oscillator is considered because it holds the potential of both high oscillation frequency and fast switch-on time. The novelty of the proposed inverter cell is found in the possibility to adjust the oscillation frequency digitally, rather than with an analog voltage. This leads to larger tuning range and less sensitivity to control noise. The digitally controlled oscillator is designed in 0.13μm CMOS technology and according to simulations the tuning range is from 4 GHz to 12.5 GHz. The power consumption is below 8 mW.

This paper presents an energy-efficient transmitter for UWB impulse-radio. The proposed circuit uses a novel combined mixer and power amplifier to generate a Gaussian pulse with 1.25GHz bandwidth and center frequency of 7.87GHz. The combined MXR-PA includes a monolithic transformer to reach a maximum output voltage swing of 3.2Vpp. The transformer has been designed so as to maximize the transmitter power efficiency and at the same time to realize a fourth-order ladder filter, in order to reduce out-of band emissions. The transmitter has been implemented in a 0.13μm CMOS technology, occupies an area of 0.14mm2and dissipates 1.92mW for a 10-pulse burst with 1.2V power supply.

A thorough analysis of the tank quality factor in LC oscillators using switched capacitor banks has been carry out taking into account the contribution of the switched capacitances in the off state. Analysis results, confirmed by circuit level simulations, clearly show that the contribution of the switched capacitances in off state strongly affects the quality factor of the capacitor bank, and thus of the tank, increasing it. General expressions of the quality factor of useful one-port reactive networks are also presented.

Shunt-shunt resistive feedback is used in this paper to design inductorless broadband LNAs in a digital 45 nm CMOS technology. Simulation results show 18 dB gain over a 10 GHz bandwidth, with NF-7 dBm in-band, while consuming 32 mW from a 1 V supply voltage.

An energy detector designed in a 0.18μm CMOS technology and intended for a non-coherent impulse-radio UWB receiver is presented in this paper. The proposed circuit exploits the quadratic current characteristic of saturated MOS transistors to square input pulses that cover the whole UWB bandwidth. The integral is computed with a Gm-C architecture connected to the squarer using a flipped voltage follower current sensor. A behavioural model of the receiver is developed in order to put the proposed circuit in the perspective of the complete system and to translate the transistor-level figures of merit in communication system parameters. The energy detector dissipates 5.4mW with a 1.8V power supply and a sensitivity of −88dBm is expected at the antenna

Trellis coded modulation (TCM) is a potential candidate for error correction in multilevel flash memories. TCM typically requires probabilistic decoding algorithms (e.g. BCJR), that can be conveniently implemented in the analog domain. In this work, we study the feasibility and complexity of the analog approach, proposing transistor-level solutions for the building blocks of the decoder. In the case of a TCM designed for an effective storage density of 3 information bits/cell, an analog decoder for a 196-bit field features an estimated current draw of2.

This work proposed to use a two-element array of coupled PLLs to generate quadrature signals. The main advantage of this technique is that phase noise performance and quadrature accuracy do not trade-off. A dual-mode quadrature VCO designed in a digital0.13μmCMOS technology is used as test vehicle to verify the viability of the proposed concept.

This work proposes an architecture for a multimode ADC. The architecture is based on the cascade of a single-bit 2-1 SigmaDelta modulator and a 4-bit flash converter. Furthermore such an architecture is mapped in a modular implementation, which allows to easily reconfigure modulator order, oversampling ratio and equivalent number of bits of the internal quantizer. As a consequence the proposed converter can fulfil the requirement of a wide range of standards: GSM, Bluetooth, UMTS and WLANa. The achieved dynamic range is 85dB, 72dB, 62dB and 59dB for GSM, Bluetooth, UMTS and WLANa, respectively. The corresponding power consumption is 4.6mW, 5.5mW, 7.4mW and 18.9mW