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Viktor Gyuris

dblp:54/5138 · DBLP profile ↗
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6ranked-venue papers
3as first author
0since 2021 · last 2000
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Theory of computation · 5 · 3 first-authorSoftware engineering, systems software and programming languages · 3 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Theoretical computer science
3 papers
Automated reasoning and model checking · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Parallel and multicore computing · 100%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Automated reasoning and model checking
model checking
0.022000
SMC: a symmetry-based model checker for verification of safety and liveness properties · ACM Trans. Softw. Eng. Methodol. 2000
On-the-Fly Model Checking Under Fairness That Exploits Symmetry · CAV 1997
Automated reasoning and model checking › model checking › state space reduction
symmetry reduction
0.021997
SMC: A Symmetry Based Model Checker for Verification of Liveness Properties · CAV 1997
On-the-Fly Model Checking Under Fairness That Exploits Symmetry · CAV 1997
Automated reasoning and model checking › temporal logic verification
safety and liveness verification
0.012000
SMC: a symmetry-based model checker for verification of safety and liveness properties · ACM Trans. Softw. Eng. Methodol. 2000
Automated reasoning and model checking › model checking › explicit-state model checking
on-the-fly model checking
0.011997
On-the-Fly Model Checking Under Fairness That Exploits Symmetry · CAV 1997
Parallel and multicore computing
concurrent programming
0.012000
SMC: a symmetry-based model checker for verification of safety and liveness properties · ACM Trans. Softw. Eng. Methodol. 2000
Automated reasoning and model checking › temporal logic verification
liveness verification
0.011997
SMC: A Symmetry Based Model Checker for Verification of Liveness Properties · CAV 1997

Methods — techniques the papers use, named apart from their topics

symmetry reduction · 0.1on-the-fly model checking · 0.1explicit state enumeration · 0.1model checking · 0.0
YearPublicationVenuePosition
2000 SMC: a symmetry-based model checker for verification of safety and liveness properties
abstract
The article presents the SMC system. SMC can be used for checking safety and liveness properties of concurrent programs under different fairness assumptions. It is based on explicit state enumeration. It combats the state explosion by exploiting symmetries of the input concurrent program, usually present in the form of identical processes, in two different ways. Firstly, it reduces the number of explored states by identifying those states that are equivalent under the symmetries of the system; this is called process symmetry . Secondly, it reduces the number of edges explored from each state, in0 the reduced state graph, by exploiting the symmetry of a single state; this is called state symmetry . SMC works in an on-the-fly manner; it constructs the reduced state graph as and when it is needed. This method facilitates early termination, speeds up model checking, and reduces memory requirements. We employed SMC to check the correctness of, among other standard examples, the Link Layer part of the IEEE Standard 1394 “Firewire” high-speed serial bus protocol. SMC found deadlocks in the protocol. SMC was also to check certain liveness properties. A report on the case study is included in the article.
A. Prasad Sistla, Viktor Gyuris, E. Allen Emerson
ACM Trans. Softw. Eng. Methodol.2
1999 Parameterized Verification of Linear Networks using Automata as Invariants
abstract
Abstract. The paper proposes an induction based approach, that employs automata as inductive invariants, for verifying safety and liveness properties of linear networks of arbitrary size. The proposed method has been shown to be complete for verifying safety properties. Automated methods that check for correcteness of such families of networks are proposed. These methods are based on generating an invariant automaton from the correctness property which is also specified by an automaton. These methods have been implemented and successfully tested on some examples.
A. Prasad Sistla, Viktor Gyuris
Formal Aspects Comput.2
1999 On-the-Fly Model Checking Under Fairness that Exploits Symmetry
Viktor Gyuris, A. Prasad Sistla
Formal Methods Syst. Des.1
1997 On-the-Fly Model Checking Under Fairness That Exploits Symmetry
Viktor Gyuris, A. Prasad Sistla
CAV1
1997 SMC: A Symmetry Based Model Checker for Verification of Liveness Properties
A. Prasad Sistla, L. Miliades, Viktor Gyuris
CAV3
1997 A Short Proof of Representability of Fork Algebras
Viktor Gyuris
Theor. Comput. Sci.1