This paper proposes a novel strategy for formally analyzing functional requirements specification (FRS) and applies it to the Automatic Train Protection and Block (ATPB) system, which is proposed to reconstruct conventional rail lines in Japan. Based on the FRS in natural language, firstly, dynamic state transitions are extracted to express the operational mechanisms and determine the system parameters. A complete model of the ATPB system is then established using Unified Modeling Language (UML) to express the system structure graphically and explicitly. After achieving a common understanding, a VDM++ model is established formally to redescribe the original FRS of the ATPB system which is written in natural language (i.e. Japanese). Following that, in order to ensure internal consistency of the specification, proof obligations of the VDM++ model are discharged. Furthermore, a comprehensive testing is implemented to ensure that the FRS meets actual requirements. Finally, the system is simulated strictly in accordance with the formal specification. Without any runtime errors, collisions or derailments, the results of the simulation demonstrate the high quality and safety of the specification.

This paper describes a system modeling method and its application to a new train control system based on the train detection COMBAT that uses radio communications. In the system modeling process, we paid attention to the function of train detection. We propose a basic model that describes the state of detecting point with three parameters. By using this model, we can define and classify the results of train detection at the detecting point before performing safety analysis. Based on this definition, we can analyze various states of the system resulting from actual train movement and state of equipment. The method we propose in this paper enables us to perform system behavior analysis systematically and efficiently and clarify the points where we should pay attention in the actual system operation.

A bus-level synchronized computer system is widely utilized in the field of railway signaling in Japan. It may be recognized that there is a problem of disadvantage in manufacturing cost reduction. We intend to integrate a bus-level synchronized FS (fail-safe) computer into an LSI chip, in expectation of cost reduction and performance enhancement. An economical FS one-chip computer utilizing system LSI technology is realized. It assures fail-safety by means of a novel fault diagnosis mechanism depending on an M-sequence code signature. These techniques are reported in detail.

The experimental results and the future plan of CARAT (Computer And Radio Aided Train control system) are presented. The experiment has been carried out on the commercial Shinkansen line over a 60 km length containing three stations from 1991. A full scale experimentation including a brake test and a recovery from various faults of system components is planned in order to verify the total safety and performance required for the practical use.>

A peripheral interface unit for a microcomputer control system fabricated by a standard n-channel silicon-gate enhancement/ depletion MOS process is described. This unit can accept analog and digital inputs, generate pulse outputs, and multiply. The analog input capability is made possible by an on-chip A/D converter using a constant slope approach with an external capacitor. This converter can perform a 10 bit conversion in 5 ms and has an input voltage range of 0-5 V with only one 8 V power supply for the analog circuits. The die area required by the converter is small and the precision analog specifications needed for the process and devices are few. The die area of the converter is 3 mm2, out of a total unit area of 35 mm2.