This paper presents a 10-b 500MS/s successiveapproximation-register (SAR) analog-to-digital converter (ADC) designed using a 40nm CMOS process. The first 6-bit coarse conversion is completed by a high speed loop-unrolled architecture, while the succeeding 5 bits are obtained by a traditional SAR structure. A foreground calibration is employed to correct the offsets in the six comparators of the coarse converter, while the residual errors due to process-voltage-temperature (PVT) variations are covered by 1-bit redundancy. A background offset calibration technique based on alternate comparators is proposed, which tracks PVT variations while eliminating a dedicated calibration phase. The spurious-free-dynamic-range (SFDR) and the signal-to-noise-and-distortion-ratio (SNDR) can achieve 60.30dB and 68.95dBc, respectively. The power consumption of the whole system is 4.164mW under 1.1V supply voltage, thereby obtaining a figure of merit (FoM) of 9.87fJ/conv.-step.

This paper presents an asynchronous 2-then-1 bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC). The offset mismatches among the three comparators are background calibrated by quantizing the same residue signal during the last 1-bit cycle. It eliminates the dependence on the signal distribution and utilizes the following sampling phase for the settling of the calibration voltages. An asynchronous timing sequence is also proposed to avoid an external high speed clock generator. A design example of 8-bit 500 MS/s SAR ADC in 40nm CMOS technology is presented. Simulation results show that with Nyquist input, the spurious-free-dynamic-range (SFDR) achieves 62 dB while the effective number of bits (ENOBs) is 7.6 bits.

This brief proposes a high spurious-free dynamic range (SFDR) pulse output direct digital frequency synthesizer (PDDS) with low complexity and low power consumption. Independent and uniformly distributed (IUD) high-pass-shaped dither is added to the phase accumulator output, resulting in a wideband spurious-free and low close-in noise floor. The power efficiency and speed are increased by reducing the sampling frequency of the${m}$-sequence generator and the high-pass filter (HPF). The SFDR improves by 29 dB as a result of the HPF, which is confirmed with a field-programmable gate array (FPGA) implementation. The application specified integrated circuit (ASIC) occupies$1168~{\mu \text {m}^{2}}$on nangate 45-nm CMOS process and consumes 80.2 and$398~{\mu }\text{W}$from a 1.2-V supply with the dither generator running at${({1}/{4})f_{\text {clk}}}$and${f_{\text {clk}}}$(${f_{\text {clk}}}=2$GHz), respectively.

This brief presents a background calibration technique for pipelined successive-approximation-register (pipelined SAR) analog-to-digital converters (ADCs), which resolves the errors from capacitor mismatches and inaccurate interstage gain errors. The dither signal is injected in the capacitor digital-to-analog converter (DAC), while its residue voltage increment is neutralized through paired comparators with opposite polarity offsets, thereby relaxing the design requirement of the residue amplifier. While one of the comparators is generating the residue signal, the other one is detecting the signal range and helping to obtain the bit weights. This brief also introduces the circuit design of paired comparators with opposite offsets. The background calibration technique is verified in a 5b + 8b pipelined SAR ADC. Simulation results show that the spurious-free dynamic range (SFDR) and the signal-to-noise and distortion ratio (SNDR) are improved from 54.5 to 94 dB and 49 to 68.9 dB, respectively. The mean value of the voltage swing increment is 34 mV with noise sources, offset, gain error, and capacitor mismatches.