We present a 45 nm half-differential 6T SRAM (HD-SRAM) with differential write and single-ended read, enabling asymmetric sizing and VTHselection. The HD-SRAM bitcell uses SRAM physical design rules to achieve the same area as a commercial differential 6T SRAM (D-SRAM). We record measurements from 80 32 kb SRAM arrays. HD-SRAM is 18% lower energy and 14% lower leakage than D-SRAM. It has a 72 mV-lower VMIN, demonstrating higher stability.

Static noise margin analysis using butterfly curves has traditionally played a leading role in the sizing and optimization of SRAM cell structures. Heightened variability and reduced supply voltages have resulted in increased attention being paid to new methods for characterizing dynamic robustness. In this work, a technique based on vector field analysis is presented for quickly extracting both static and dynamic stability characteristics of arbitrary SRAM topologies. It is shown that the traditional butterfly curve simulation for 6T cells is actually a special case of the proposed method. The proposed technique not only allows for standard SNM ¿smallest-square¿ measurements, but also enables tracing of the state-space separatrix, an operation critical for quantifying dynamic stability. It is established via importance sampling that cell characterization using a combination of both separatrix tracing and butterfly SNM measurements is significantly more correlated to cell failure rates then using SNM measurements alone. The presented technique is demonstrated to be thousands of times faster than the brute force transient approach and can be implemented with widely available, standard design tools.

This paper describes critical circuit building blocks for emerging sensing applications, particularly those where volume, and therefore power consumption constraints are orders of magnitude below current state of the art. Developments in ultra-low power microprocessors and memories are described, along with sub-nW timekeeping circuits, pW voltage references, and efficient DC-DC voltage conversion circuits at sub-μA current loads. Taken together, these circuit design advances point to a vision of true mm3low-cost sensing nodes with hybrid power sources, i.e., scavenged and micro-battery, providing long lifetime and reliable operation.

Power has become the primary design constraint for chip designers today. While Moore's law continues to provide additional transistors, power budgets have begun to prohibit those devices from actually being used. To reduce energy consumption, voltage scaling techniques have proved a popular technique with subthreshold design representing the endpoint of voltage scaling. Although it is extremely energy efficient, subthreshold design has been relegated to niche markets due to its major performance penalties. This paper defines and explores near-threshold computing (NTC), a design space where the supply voltage is approximately equal to the threshold voltage of the transistors. This region retains much of the energy savings of subthreshold operation with more favorable performance and variability characteristics. This makes it applicable to a broad range of power-constrained computing segments from sensors to high performance servers. This paper explores the barriers to the widespread adoption of NTC and describes current work aimed at overcoming these obstacles.

A minimum area portless SRAM cell is presented along with a stunted wordline driver. When compared to an iso-area 6T cell using logic design rules, the portless cell exhibits 22% higher static noise margin and 14% lower leakage with a 51% penalty in the on/off cell current ratio. Measurements from a fabricated test chip in 0.5 mum CMOS demonstrate functionality of the proposed cell and driver in an array, and for the first time, validate the portless concept in an isolated test cell.

A Self-Biased Charge-Transfer Sense Amplifier (SB-CTSA) is proposed for applications in high performance static memory. The new design incorporates an internal biasing mechanism along with a static output latch that can store the result from a read cycle indefinitely at no additional cost in power. It exhibits 23% faster sensing delay and a 37% reduction in read energy when compared to a recently proposed CTSA structure. In addition, the SB-CTSA design exhibits low sensitivity to both input capacitance and input capacitance mismatch.