Network-on-chip based many-core processors break the limitations faced with single-core processors, and can bring high performance, improved yield, and high reliability. They are widely considered as the most promising platform. One of the most important questions is: what kind of granularity of cores (in other words, the number of cores and the area of each core under specific area constraint of the chip) is the best for many-core processors? Performance is widely used as the most important metric to determine the choice, but recently, reliability and yield are also becoming the first-class constraints in many application domains. This paper presents a novel performance model by considering practical program style, including pipelined and parallel program styles, as well as intercore communication, and proposes a new metric combing performance, reliability, and yield of many-core processors to choose the core granularity. According to our paper, with a given area (300 mm2) and certain applications, the optimal result is obtained using 8 × 8 mesh when all three factors are considered.

Performance is one of the most important targets in MPSoC design, and it is affected by a lot of factors, such as area, yield, application, and lifetime. Based on the performance, yield and lifetime reliability modeling and analysis of MPSoC, this work proposes a metric directing how to choose the granularity of MPSoC at high level design in order to obtain high performance when yield and lifetime reliability are considered. The results show that, with the given area (300mm2) and certain applications, the optimal performance is obtained at 3×3 mesh, and optimal design becomes 4×4 mesh when yield is considered, and it will prefer 5×5 mesh or 6×6 mesh when lifetime reliability is further considered.

There is a growing interest in designing high-performance network devices to perform packet processing at flow level. Applications such as stateful access control, deep inspection and flow-based load balancing all require efficient flow-level packet processing. In this paper, we present a design of high-performance flow-level packet processing system based on multi-core network processors. Main contribution of this paper includes: a) A high performance flow classification algorithm optimized for network processors; b) An efficient flow state management scheme leveraging memory hierarchy to support large number of concurrent flows; c) Two hardware-optimized order-preserving strategies that preserve internal and external per-flow packet order. Experimental results show that: a) The proposed flow classification algorithm, AggreCuts, outperforms the well-known HiCuts algorithm in terms of classification rate and memory usage; b) The presented SigHash scheme can manage over 10M concurrent flow states on the Intel IXP2850 NP with extremely low collision rate; c) The performance of internal packet order-preserving scheme using SRAM queue-array is about 70% of that of external packet order-preserving scheme realized by ordered-thread execution.

In this paper, a novel packet classification scheme optimized for multi-core network processors is proposed. The algorithm, Explicit Cuttings (ExpCuts), adopts a hierarchical space aggregation technique to significantly reduce the memory usage. Consequently, without burst of memory usages, the time-consuming linear search in the conventional decision-tree based packet classification algorithms is eliminated, and an explicit worst-case search time is achieved. To evaluate the performance of ExpCuts, we implement the algorithm, as well as HiCuts and HSM, on the Intel IXP2850 network processor. Experimental results show that ExpCuts outperforms the existing best-known algorithms in terms of memory usage and classification speed.

Next-generation high-end network processors (NP) must address demands from both diversified applications and ever-increasing traffic pressure. One major challenge is to design an extraordinary scalable architecture. In this paper, it is argued that such an objective can only be sufficed by introducing highly paralleled structure, namely the paralleled processing-engine cluster (PPC). We demonstrate this point from the trade-off among aspects such as performance, programmability and flexibility. However, PPC natively suffers from several critical issues on load-balancing, intra-flow packet ordering and memory contention. After investigating several existing approaches, we present novel solutions for each issue according to the balance between performance and coast. Through intensive analysis and comprehensive simulations, it is shown that the shortest queue first scheduling with class-based prediction (SQF-C) performs nearly optimally, while the hardware based per-flow ordering mechanism resolves packet out-of-order independently with the load-balancing issue, inducting little throughput degradation. Implementing the unified solution, it is capable to design a PPC supporting up to OC-768c line rate. Real implementation is also carried out in our THNPU-1 prototype to verify the conclusions.