Various cryptosystems, such as elliptic curve and pairing‐based cryptosystems, in resource‐constrained security applications rely on finite field multiplication. For applications such as these, a digit‐serial multiplier has the potential features to achieve a trade‐off between space and time complexities. The authors propose an efficient decomposition of the multiplication into four independent sub‐multiplication units to facilitate parallel processing, which is additionally facilitated by the systolic structures of the sub‐multiplication units. The proposed architecture uses a four‐bit scheme to construct a novel processing element, instead of using only one bit as is currently used in similar multipliers. The results of the synthesis show that the proposed digit‐serial dual basis multiplier eliminates up to 96% of the critical path delay.

Recently in cryptography and security, the multipliers with subquadratic space complexity for trinomials and some specific pentanomials have been proposed. For such kind of multipliers, alternatively, we use double basis multiplication which combines the polynomial basis and the modified polynomial basis to develop a new efficient digit-serial systolic multiplier. The proposed multiplier depends on trinomials and almost equally space pentanomials (AESPs), and utilizes the subquadratic Toeplitz matrix-vector product scheme to derive a low-latency digit-serial systolic architecture. If the selected digit-size is$d$bits, the proposed digit-serial multiplier for both polynomials, i.e., trinomials and AESPs, requires the latency of$2\left\lceil \!{\sqrt {{m \over d}}} \right\rceil\! $, while traditional ones take at least$O\left({\left\lceil {{m \over d}} \right\rceil} \right)$clock cycles. Analytical and application-specific integrated circuit (ASIC) synthesis results indicate that both the area and the time$ \times $area complexities of our proposed architecture are significantly lower than the existing digit-serial systolic multipliers.

Multiplication is one important finite field arithmetic operation in cryptographic computations. Dual basis multipliers over Galois field GF(2 m ) have been widely applied in this kind of computations because of its advantage of small chip area. Nevertheless, up to date, there are only few methods that can keep balance of low space complexity and low time complexity at the same time. In order to achieve such an efficient aim, this study presents a novel digit‐serial dual basis multiplier that is different from existing ones with a modified cut‐set method using Karatsuba algorithm as well as Hankel matrix. As a result, the proposed multiplier can save much space and thus be particularly suitable for some hand held devices equipped with only limited resources. The proposed digit‐serial dual basis multiplier saves 55% space complexity as compared with existing similar studies with National Institute of Standards and Technology (NIST) suggested values for elliptic curve cryptosystem.

The elliptic curve cryptosystem (ECC) is very attractive for the use in portable devices because of the small key size. The finite field multiplication over GF(2m) is the most important arithmetic for performing the ECC. Portable devices usually have restricted computation power and memory resources. This work will present a simple method for designing a Gaussian normal basis (GNB) multiplier over GF(2m) needing only fewer computation power whereas keeping lower cost. The proposed Gaussian NB multiplier saves ∼57% space complexity as compared with existing GNB multiplier.

Palindromic representation is generally used to reduce space and time complexities in Gaussian normal basis (GNB) multiplier with even type t. However, palindromic representation is inapplicable for a GNB multiplier with odd type t ($t \geq 2$). This study therefore develops a palindromic-like representation for a GNB multiplier with odd type t. The proposed systolic GNB multiplier with odd type t reduces space and time complexities by as much as 50% compared with conventional GNB multiplier with odd type t without palindromic representation.

Fault-tolerant design of a finite field multiplier is an efficient method for resisting fault-based cryptanalysis in Elliptic curve cryptosystems. A novel fault-tolerant bit-parallel Gaussian normal basis (GNB) multiplier with type-t over GF(2m), which can tolerate multiple module failures at one time, is presented. No hardware modification in the proposed GNB multiplier is required to achieve the fault-tolerant function. Hence, the proposed fault-tolerant GNB multiplier has low hardware cost. The reliability of the proposed fault-tolerant GNB multiplier with type-t increases as t increases. However, the behaviour of existing GNB multipliers with concurrent error correction (CEC) resembles triple modular redundancy (TRM) when t>3. In practice, most of suggested m's by NIST use GNB with type-t>3. The proposed fault-tolerant GNB multiplier is an N-modular redundancy (NMR) system with N=t. Thus, the proposed fault-tolerant GNB multiplier with type-t can tolerate at most t/2-1 failed modules simultaneously, while existing GNB multipliers with CEC only can tolerate one failed module. The proposed GNB multiplier requires less extra space and time complexities than similar multipliers. System reliability of the proposed fault-tolerant GNB multiplier is better than that of similar GNB multipliers.

Recently, information security is heavily dependent on cryptosystems such as Rivest-Shamir-Adleman algorithm (RSA algorithm) and elliptic curve cryptosystem (ECC). RSA can provide higher security level than ECC, but it is not suitable for the resource-constrained devices such as smart phones or embedded system. Thus, ECC is attracted on application in resource-constrained devices because it can achieve the same security level, but uses less key length than RSA. Galois or finite field multiplication is the core arithmetic operation of ECC. There are three popular bases in the finite field over GF(2m), polynomial basis, normal basis and dual basis (DB). Each basis representation has its own advantages. In this study, the authors will introduce a low-complexity bit-parallel DB multiplier using the multiplexer approach. Compared with the related work, our design saves up to 60% of space complexity.

This work develops a novel self-checking alternating logic (SCAL) bit-parallel Gaussian normal basis (GNB) multiplier with type-t over GF(2m). The proposed GNB multiplier is with both concurrent error-detection and off-line testing capabilities. The concurrent error-detection capability can give countermeasure to fault-based cryptanalysis. The off-line testing capability supports the design-for-test property. The proposed SCAL GNB multiplier can detect both permanent and transient faults. The proposed SCAL GNB is the first normal basis multiplier to have both on-line error-detection and off-line testing capabilities.

Finite field arithmetic has been widely used in many cryptosystems, particularly in the elliptic curve cryptosystem (ECC) and the advanced encryption standard (AES) as a method for speeding up their encryption/decryption processes. Low-cost design for finite field arithmetic is more attractive for various mobile applications. It is a factor that a large number of Exclusive OR (XOR) gates have been used in the arithmetic operations under the traditional finite field arithmetic implementation. Thus, the cost of the traditional finite field arithmetic cannot be effectively lowered, because a typical XOR gate design consists of 12 transistors. To address this, a novel non-XOR approach consisting of eight transistors, for realising low-cost polynomial basis (PB) multiplier over GF(2m) was developed in this study. The authors proposed that non-XOR architecture for bit-parallel PB multiplier uses the multiplexer function instead of the traditional XOR function in its design. Based on the proposed non-XOR methodology, three popular low-cost irreducible polynomials – trinomial, pentanomial and all-one-polynomial – are proposed and designed in this study. The results indicate that the proposed non-XOR architecture can reduce space complexity by 22%, compared with that of the traditional design.

Finite-field arithmetic has been widely used to speed up the encryption and decryption processes in many cryptosystems, especially elliptic curve cryptosystems. Regular finite-field arithmetic structures are suitable for very large-scale integration implementation of cryptosystems, making them attractive for mobile commerce applications. Multiplication is the critical operation in finite-field arithmetic operations. Fault-based cryptanalysis is a new cryptanalysis method that deliberately injects faults into cryptographic devices, and requires only a small amount of side-channel information to break common ciphers. Thus, effective and simple methods for protecting the encryption/decryption circuitry from attackers are required to ensure that cryptographic devices can produce accurate signatures. This study presents a polynomial basis (PB) multiplier over GF(2m) with concurrent error detection (CED), and proposes a PB multiplier with concurrent error correction (CEC). A parallel structure of function cells is used in the proposed multiplier array to reduce the propagation delay. The proposed PB multiplier with internal parallel structure can reduce the time complexity by 28%, and reduce the space complexity by 90%, compared with existing PB multipliers. Compared with existing PB multipliers with CED, the proposed device with CED has a 20% greater space complexity but a 30% less time complexity. To the author's knowledge, there is no previous report of PB multipliers with CEC capability. The proposed PB multiplier with CEC capability has a space complexity of only about 10% more and requires five more clock cycles than the proposed device without CEC capability.

Euclid's Greatest Common Divisor (GCD) algorithm is an efficient approach for calculating multiplicative inversions. It relies mainly on a fast modular arithmetic algorithm to run quickly. A traditional modular arithmetic algorithm based on nonrestoring division needs a magnitude comparison for each iteration of shift-and-subtract operation. This process is time consuming, since it requires magnitude comparisons for every computation iteration step. To eradicate this problem, this study develops a new fast Euclidean GCD algorithm without magnitude comparisons. The proposed modular algorithm has an execution time that is about 33% shorter than the conventional modular algorithm.

A scalable unified multiplier for both prime fields GF(P) and binary extension fields GF(2k), where P=2m−1 and GF(2k) is generated by an irreducible all one polynomial. The proposed unified dual-field multiplier uses the LSB-first bit-serial architecture for multiplication in GF(P) and GF(2k) other than the Montgomery multiplication algorithm, which has been employed by most existing dual-field multipliers. The proposed unified dual-field multiplier costs little space and time complexities. The new multiplier is scalable for operands of any size while other existing dual-field multipliers are only scalable for operands with multiples of m. Furthermore, the proposed multiplier has simplicity, regularity, modularity and concurrency and is very suitable to be implement in VLSI.

Fault-based cryptanalysis has been developed to effectively break both private-key and public-key cryptosystems, making robust finite field multiplication a very important research topic in recent years. However, no robust normal basis multiplier has been proposed in the literature. Therefore, this investigation presents a semisystolic Gaussian normal basis multiplier. Based on the proposed Gaussian normal basis multiplier, both concurrent error detection and correction capabilities can be easily achieved using time redundancy technology with no hardware modification.