It is observed that the Engineering students are coming in with weakness in problem solving skills. For example, in Electric Circuits I course, they are able to apply principles of Ohm’s Law, Kirchhoff’s laws, mesh and nodal analysis techniques. However, they can obtain the solution of resulting simultaneous equations correctly 80% of the time. They are making mistakes in solving two or three variable algebraic simultaneous equations. Therefore, 90% of mistakes are in calculation of unknown variables. This is also true in Electric Circuits II course where they have difficulties in applying calculus and differential equations. This type of weakness exists in all branches of engineering. One way is to actively engage students with some intervention. We have designed an intervention mechanism and have been experimenting for the last two years. This paper describes intervention experiment and results from tracking of their cumulative GPAs for three-year period.

The nation is reaching at a critical stage due to shortage of Science Technology Engineering Mathematics (STEM) related workers. The shortage is felt across all government agencies and private sector. High tech industry is bringing foreign workers via H1B program to fill their needs. This is creating a challenge within the country and becoming a national security issue. One way to keep students in the STEM field is to increase recruitment, retention, and graduation rate. This paper is focused on providing one experiment to achieve above goals.

It has been reported that incoming students are weak in Mathematics and thereby having great difficulty in engineering courses. As a result, they are dropping out of engineering programs resulting in low retention and graduation rates. It is desired to reinforce mathematical concepts in gateway courses. One way is to engage them via additional informal instruction sessions, peer mentoring research projects. Our experiment with five activities of offering Saturday Academy, peer mentoring, professional lecture series, freshman seminar and summer research projects has been running for two semesters. Results are preliminary and future looks optimistic.

Cognitive radio (CR) technology offers the possibility of an increase in spectrum utilization efficiency to resolve the prevalent spectrum scarcity problem. The economic survival of secondary spectrum markets (SSMs) is heavily dependent on the sharing of both the licensed spectrum and spectrum infrastructure by primary licensed operators (PLOs). In this research, an automated pricing model using a blockchain token called the spectrum dollar has been implemented for secondary radio spectrum trade. The use of spectrum dollars enables noncash-based secondary spectrum trade among PLOs based on a floor-and-trade rule. The pricing of spectrum dollars and the associated revenue shares are based on the underlying secondary spectrum trading behaviours of PLOs. PLOs that do not contribute enough secondary spectra to the SSM (to satisfy demand) suffer a loss proportional to the difference between their earned revenues and the specified floor value in the SSM. The secondary spectrum trade is assumed to be centrally managed by a spectrum broker, which announces the floor value for each bidding period while ensuring nonnegative revenue for the market itself. The use of the spectrum dollar along with the floor-and-trade methodology eliminates the possibilities for economic malpractice by PLOs that could increase spectrum reuse costs. In addition, the floor value provides automatic regulatory control to ensure the economic viability and prevent the technological hijacking of future SSMs.

This paper presents an automatic VHDL generator for a modified fixed-point interpolation QR decomposition algorithm for Spherical Detector (SD) based Multiple-Input Multiple-Output (MIMO) Orthogonal Frequency Division Multiplexing (OFDM) systems. A modified algorithm is proposed that moves the bulk of the complex domain calculations to the real domain, by leveraging Givens rotations requiring only additions, multiplications, and inverse square root operations. An efficient inverse square root algorithm is presented along with fixed-point analysis of a typical MIMO-OFDM system in various noisy wireless channels. Autogeneration of VHDL modules is described with results of 2 × 2 and 4 × 4 QR-based SD MIMO detection in terms of FPGA slice registers and slice LUTs.

Nocturnally migratory birds and bats are at higher risk of colliding with wind turbines. It is important to gather scientific data in an area which have potential of wind farm development. An IR camera recording and its analysis can provide necessary information to wildlife biologists involve with interaction of birds/bats with wind turbines. An efficient IR video processing algorithm has been developed. The proposed algorithm consists of background and consecutive frame subtraction, frame selection, 3-D region labeling and breakpoint recovery. It is then used to process spring 2011 bird migration data that has been collected in Ottawa National Wildlife Refuge in Ohio. Results from this study will be useful for wildlife biologists to make intelligent decision for siting of wind turbines. It will also help policy makers to develop an appropriate public policy for wind farm development in an area with extensive avian activity.

Acoustic monitoring of birds in the vicinity of wind turbines is becoming an important public policy issue. Acoustic monitoring involves preprocessing, feature extraction and classification. A novel Spectrogram-based Image Frequency Statistics (SIFS) feature extraction algorithm has been developed. Features extracted from proposed algorithms were then combined with various classification algorithms such as k-NN, Multilayer Perceptron (MLP) and Hidden Markov Models (HMM) and Evolutionary Neural Network (ENN). SIFS and MMS algorithms, combined with ENN, provided the most accurate results. Proposed algorithms were tested with real data collected during spring migration around Lake Erie in Ohio.

An Evolutionary Neural Network (ENN) is developed to identify bats by their vocalization characteristics. This is in an effort to identify local bat species as a large number of bat fatalities near wind turbines have been reported. ENN is based on the Genetic Algorithm, which can be used for optimization of the weight selection of the neural network. We then compare ENN with different classification techniques. In the scope of bat call classification, ENN is a new technique that can be effectively used as a bat-call classifier. This research will help in developing mitigation techniques for reducing bat fatalities. The ENN algorithm is developed in MATLAB.

This paper presents a unique scheme for testing and locating multiple stuck at faults in the embedded RAM modules of SRAM-based FPGAs. The RAM modules are tested using the MATS++ algorithm. The interconnection scheme makes it possible to test all the cells within the RAM modules in the FPGA in just one test configuration. A diagnosis scheme capable of locating the faulty RAM cell and the CLB in which it is located is also developed.Considerable research in the area of testing the LUT/RAM modules for SRAM based FPGAs has been done earlier. However, the solutions proposed are not optimal as they require N test configurations to test an N input RAM module. One such solution proposes a Pseudo Shift Register (PSR) interconnection scheme using the shifted MATS++ algorithm. It is possible to test all the RAM modules in an FPGA in one test configuration using this approach. However, although this scheme can detect the faulty cell in the RAM modules under test, it does not have the capability of locating the faulty CLB in which the RAM modules are located. In other words, the scheme assumes that the faulty CLB is known. This drawback is eliminated in the scheme presented in this paper by using a unique interconnection of CLBs in the form of a chain. In addition, the proposed interconnection scheme also reduces the testing time by approximately half as compared to the time taken by earlier schemes. The FPGA is modeled in VHDL at the equivalent gate level and the simulations results are generated using ModelSim.

A high speed 800 channel digital interpolator network has been designed. The interpolator network accepts data from the demultiplexer onboard a satellite which separates 800 telephone channels from ground stations in an FDMA format into individual channels in a TDM format at 45 ksamples/sec/ch. The interpolator then changes the sampling rate of the data input to 64 ksamples/sec/ch so that the demodulator onboard the satellite can correctly demodulate all of the 800 channels with a requirement of two samples/symbol data rate. An interpolator network has been implemented using 0.8 micron CMOS technology and is suitable for real time processing.

A generalized covariance matrix computation processor has been designed. The covariance matrix is the first processing step for the computation of the direction of arrival (DOA) algorithms. This covariance processor is useful for computing the covariance matrix for various DOA algorithms. In this work three DOA algorithms namely MUSIC algorithm for narrowband signal and BASS-ALE & bilinear transformation algorithms for wideband signals have been considered. The processor has been implemented using 0.8 micron CMOS technology and is suitable for real time processing.>

In this paper, the design and analysis of a mesh-type systolic array architecture for computing the Single Linkage (SLINK) algorithm is presented. This algorithm is frequently used in hierarchical clustering applications. However, since the algorithm is iterative in nature, it takes considerable CPU time for processing. This makes the algorithm unattractive for real-time applications. The systolic array, described in this paper, increases the speed of computation of the algorithm.>

A reconfigurable transmultiplexer that is capable of on-board demultiplexing of a varying number of single channel per carrier frequency division multiple access (FDMA) channels with varying bit rates is presented. The multiplexing algorithm selected for demultiplexing the FDMA channels is the polyphase FFT (fast Fourier transform) method, which requires a bank of filters followed by an FFT operation. A reconfigurable shared filter bank and reconfigurable pipelined FFT architecture are designed to implement the bank of filters and FFT operations for two different cases. The architecture is suitable for satellite on-board processing as it is reconfigurable and modular and can perform its processing in real time without large buffers. The architecture is illustrated specifically for demultiplexing 800 channels, at 64 kbps or a mix of 400 channels at 64 kbps and 12 channels at 2.048 Mbps or 24 channels at 2.048 Mbps.>

A real-time vector quantizer (VQ) architecture for broadcast quality encoding of color TV images is presented. The architecture maps the mean/quantized residual vector quantizer (MQRVQ), an extension of mean/residual VQ, onto a VLSI/LSI chip set. The MQRVQ contributes to the feasibility of the VLSI architecture through the use of a simple multiplication-free distortion measure and reduction of the required memory per codevector. In other words, the complexity-reduced MQRVQ allows each subcodebook of 128 codevectors (10 kb) and its associated encoding elements to be fitted onto a VLSI chip. This architecture reduces encoding search complexity through partitioning of a large codebook into on-chip memories of a concurrent VLSI chip set. There are 64 of these VLSI chips to accommodate a codebook with size up to 2/sup 13/=8192 codevectors. The architecture is capable of real-time processing of 480*768 pixels per frame with refreshing rate of 30 frames/second.>

A data flow general purpose digital signal processor has been previously developed [1] for real time applications of digital signal processing. The Data Flow Signal Processor (DFSP) is attached to a host computer, and is based on a binary tree structure. It employs two types of cells: processing and arithmetic cells, and utilizes residue number system [2] for arithmetic operations. The objective of this work is to develop architecture of the processing cell [3]. This processing cell is simulated on a VAX 11/785 computer system utilizing A Hardware Programming Language (AHPL) [4]. Simulation results shows that processing cell architecture is valid and DFSP is capable of high throughput rates. This paper describes structure and operation of the processing cell.

A real time general purpose signal processor architecture has been developed previously [1,2]. This architecture utilizes parallel, pipeline and distributed processing approaches to achieve high speed computation. Software techniques for programming the data flow signal processor are presented since conventional programming languages are not suitable for programming fast parallel machines. Data flow graphs (DFG) are used to develop an interactive programming environment which will shield the programmer from the internal structure of the data flow signal processor (DFSP). The programming of the DFSP is demonstrated with an image processing application. This example illustrates that the direct convolution can be used to perform computations at video rates.

A design of real time general purpose signal processor architecture is proposed in this paper. The processor is based upon a binary tree structure utilizing multiprocessing, pipeline and distributed processing techniques. A host computer distributes the individual tasks to each processor to perform parallel operations. The residue number system is used for carry free arithmetic operations stored in RAM's and to achieve smaller packet size, eliminating serial transmission of packets as proposed in other data flow machines. The processor is programmable and capable or performing real time signal processing operations.