Particle therapy and FLASH radiotherapy offer promising advancements in cancer treatment. However, accurately measuring radiation dose within the body, especially in real-time and high dose rates characteristic of FLASH radiotherapy, poses significant technological challenges. Ionoacoustic methodologies offer an innovative and non-invasive approach to particle therapy dosimetry, leveraging the generation of acoustic waves from energetic particle interactions. As the initial pressure distribution of a ionoacoustic wave is linearly proportional to the absorbed dose, it is possible to reconstruct the dose distribution from the acoustic signals. This work explores the viability of ionoacoustic dosimetry through computational simulations of 9 MeV FLASH electron beams using the k-Wave toolbox in MATLAB with a variable number of sensors with the goal of maximizing the gamma index with a 1%/1 mm standard. Two different imaging algorithms were compared, and the results clearly indicate that interpolated time reversal (ITR) outperforms standard time reversal (STR) across virtually all sensor configurations. Remarkably, ITR achieves high-quality image reconstruction with a significantly lower number of sensors. For instance, using ITR acceptable images (above 90% of the gamma index less than 1) were produced with as few as 24 sensors, 78% less than the ones necessary for STR, which required at least 108 sensors to reach a similar accuracy of 90.75%. When using 108 sensors, ITR demonstrated a 99.80% accuracy, representing an improvement of 46.25 times over STR.

This paper presents a continuous time voltage amplifier based on a classical MOS Transistor (MOST) input differential stage feeding a regulated cascode output stage. One of the most interesting aspects of the presented circuit is the introduction of complex conjugated poles in the output stage which together with a simple R-C network at the input of the differential stage allows to synthesize a 3rd-order low-pass Butterworth transfer function at 20 dB of passband gain. The proposed circuital technique has been validated by the design of a 3rd-order low-pass filter and amplifier in 28 nm CMOS technology. The proposed circuit has 5.2 nV/√Hz in-band Input Referred Noise (IRN) Power Spectral Density (PSD), −3.2 dBm Input 3rd-order Intercept Point (IIP3) at 20 dB passband gain and a final Signal-to-Noise-Ratio (SNR) of 60 dB. This solution is particularly efficient in terms of both power consumption and linearity while performing large SNR, as demonstrated by the final Figure-of-Merit of 159.2 dBJ−1.

This paper presents the design and experimental characterization of a Proton Sound Detector (ProSD), a device that physically captures and senses the weak acoustic signal emitted by the fast energy deposition at the end of the same proton beam range. The measured acoustic signal Time-of-Flight provides a very accurate (13 μm accuracy) measure of the proton beam penetration depth in water, improving the proton range verification accuracy w.r.t. previous works in pre-clinical scenarios. This suggests interesting possibilities for high-accuracy and real-time beam monitoring and calibration in hadron-therapy for cancer treatment. The detector has been fully characterized and tested with a physical 20 MeV proton beam in a water energy absorber. The ProSD and the water tank have been mounted in front of the exit layer of a 20 MeV 120 ns pulse time-width proton beam. A clear sinusoidal-like acoustic signal of 5 Pa and 2.3 MHz frequency has been detected at 12 dB SNR with 0.8 Gy single shot dose. After averaging 10 beam shots the achieved Signal-to-Noise-Ratio is 22 dB allowing a ±7.5 μm precision vs. previously reported ±45μm ionoacoustic precision.

The synergy between schematic and layout to optimize the performance of analog circuits in scaled technologies is addressed for the case of an innovative analog filter, developed in the 28nm node. This benchmark is a 75MHz 4th-order low-pass analog filter in 28nm-CMOS composed by two Active-RC Rauch biquadratic cells. The architecture is customized to properly operate in the challenging conditions of low VDD(0.9V) and low [VDD-VTH] space (≈ 0.4V) and overcoming the poor analog performance of the 28nm MOS devices. In these directions, aggressive opamp input and output CMFB are applied. The paper shows how layout could corrupt the high-frequency performance of the filter without specific solutions. Optimized and synergic design and layout solutions are validated by the experimental results. The filter consumes 2.68mW from a single 0.9V-VDD. 11.5dB IIP3 at 20&21MHz and 40dBc of THD at 20MHz, respectively are achieved, while performing 310µVRMSof integrated in band noise.

In this paper a 75MHz 4thorder low-pass analog filter in CMOS-28nm is presented. The filter is composed by the cascade of two Active-RC Rauch biquadratic cells. The hereby proposed design manages a very low Vdd/Vth ratio (<;2) for Standard-Process (SP) MOS transistors by means of a dedicated input Common-Mode (CM) feedback circuit (I-CMFB), that operates the OPAMP input differential pair in weak inversion region independently on common mode variations. The single Rauch cell exploits a feed-forward compensated OPAMP, where an improved output CM feedback (O-CMFB) circuit has been adopted reducing this way the parasitic poles of the CM loop, and improving O-CMFB phase margin. The OPAMP has been designed using a folded topology for stable operating point. The design prototype achieves 75MHz-3dB frequency at 2.8mW power consumption from a single 0.9V supply voltage, including also I-CMFB and O-CMFB power. In-band integrated noise is 320uVrms. The filter performs 20dBm and 13dBm IIP3 at 6&11MHz and 50&55&MHz, respectively. Thanks to the very large linearity achieved at edge of the signal pass-band this design has one of the highest Figure-of-Merit for Active-RC filters.

This paper presents the design of a 4th-order closed-loop continuous-time filter. This filter exploits an improved analog stage that makes linearity performance constant over the entire pass-band frequencies. In other words the filter has same IIP3 at low and at high frequency. Hence the linearity performance are independent on the input tones bandwidth, whereas most of analog filters suffers from poor linearity when loop-gain reduces, i.e. close to the closed-loop poles frequency. In order to validate the hereby proposed design idea a 4th-order 25MHz-3dB bandwidth pseudo-differential filter has been designed and simulated in CMOS 28nm technology. The prototype consumes 820μW from 1V supply voltage and has 15dBm and 13dBm IIP3 at 5&6MHz and 20&21MHz input tones, respectively.

A 4th-order 28.8MHz low-pass analog filter uses a modified version of Sallen-Key (SK) biquad that solves the standard SK cell critical aspect due to the out-of-band zeros (OoB). The proposed cell completely cancel the OoB zeros by means of a low-power auxiliary path and a specific design optimization.

This paper presents a 4th-order low-pass continuous-time filter with 21.4 MHz bandwidth. Using a positivefeedback in combination with resistors, this architecture synthesizes two complex conjugate poles. The filter is designed and optimized to feature high-linearity along all filter passband, and, in particular, at the cut-off frequency edge. The filter consumes only 100 μA with 1.8V voltage supply, and achieves 45μW/pole power consumption, 300 μVRMSinput-referred noise, 21.9 dBm IIP3 with 2–3 MHz input tones and 12dBm IIP3 near the cut frequency using 19–20 MHz tones.

This paper presents GEMINI, an entire read-out System-on-Chip (SoC) to be used with the Triple Gas-Electron Multiplier (GEM) detector. Designed in CMOS 180 nm technology, GEMINI pushes towards the state-of-the-art for this peculiar detector front-end, as regards the count rate and detector pixel parasitic capacitance sustainability. It is composed of 16 channels, each performing a charge-to-voltage conversion via a Charge-Sensitive Preamplifier (CSP), a successive event discrimination with channel-independent threshold and an event-triggered reset. The CSP analog output and the LVDS discriminator output are available as chip outputs for each channel. The Q-to-V conversion accuracy is guaranteed by an automatic on-chip calibration unit, compensating for environmental, CMOS process and supply voltage variations. GEMINI is able to sustain a 5 Mcps count rate, managing up to 40 pF pixel capacitance and with a 2.7mW/ch power consumption.

In this paper a highly linear-dual band RF front-end (LNA and Mixer) for IR-UWB (IEEE 802.15.4a) applications is proposed. LNA exploits a common-gate (CG) stage in parallel to a common-source (CS). It performs single-ended to differential-ended operation, avoiding balun stage. It features 18 dB maximum gain,+11.8 dBm IIP3. The RF front-end receiver has been designed in 65nm CMOS technology consuming 13.5 mW.

The design of an automatic biasing system for High-Electron-Mobility-Transistors is here presented (HEMT-Biasing-System, HBS). The HBS automatically regulates the operating point of an off-chip multistage HEMT block. A proper automatic algorithm is implemented in order to maximize the HEMT transconductance (gm) efficiency (defined as gm/IDSratio). This is an important feature in several HEMT-based systems, since they are used in LNA stages, where noise/power trade-off is a key aspect. Interfacing CMOS and HEMT technologies features several design issues, like negative gate-source voltage (to be managed by a CMOS circuits for HEMT switch-off operation) and closed-loop stability (due to the presence of very large off-chip capacitance - 100nF). The System here presented manages all these issues with tailored circuit solutions. A prototype has been designed in CMOS 0.35μm technology. It consumes 6.2mW (excluding the current consumption for HEMT driving).

In this paper a 5thorder low-pass continuous time analog filter in CMOS 45nm technology is presented. The filter design is based on a single compact cell used to synthesize five poles. The circuit performs the low-pass filtering of the in-band signal, while the in-band thermal noise is high-pass filtered, improving Signal-To-Noise-Ratio. 1-GHz -3dB-bandwidth is obtained by a prototype of the filter simulated in 45nm CMOS technology node (also Process-Voltage-Temperature simulations are available). The overall power consumption is 9mW from a single 1.2V supply voltage. 54dB@THD>40dBc is the SNR at 0dB gain.

In this paper the complete design of a Programmable Gain Amplifier embedded in UWB receiver is presented. The receiver is part of a System-On-Chip placed inside the car tire (with the aim to interchange data with the car control unit) where dynamic stress, temperature and aging are very important issues, resulting in severe design constraints for CMOS analog integrated circuits. Furthermore, the SoC is biased by vibration-based energy scavenger, and a as consequence, very low power is available for the integrated circuits. High input impedance is required from system level constraints and this is achieved with MOS input devices, exploiting dual differential input Opamp. The PGA gain is programmable in the 15dB-to-50dB range with 1dB step. For the maximum gain level (50dB), the Input-Referred-Noise power spectral density is lower than 20nV/vHz. From a single 1V supply, for the minimum gain level (15dB), a 0.8Vzero-peak output signal is processed with THD=−40dBc.

In this paper a 11MHz-f@-3dBcontinuous-time analog filter is presented. A low-noise circuital topology has been used based on typical Active-RC cells, like opamp-based integrators, and Active-Gm-RC biquadratic cell. The basic idea is to synthesize two complex poles pairs (4th-Order Filter) using a single compact Active RC cell, which minimizes the in-band noise power contributions. A filter prototype, complying with WLAN baseband requirements, has been designed in CMOS 90nm technology. Thanks to noise power spectral density reduction - 48μVrmsoutput integrated noise (100kHz÷11MHz) at 0dB-pass-band gain - wide Dynamic Range (84dB@THD>;40dBc) is performed. In-band IIP3 is 10dBm, while the filter power consumption is 14mW.

In this paper two different design approaches for a large tuning range LP filter for DVB-T receivers are presented. The LP filter is placed at the beginning of the receiver chain, before to the RF and base band blocks, so that the design is challenging because high out-band frequencies rejection is required while maintaining low input referred noise. Closed-loop topologies have been investigated to comply with the in-band linearity requirements. A system level analysis has been developed using a proper Matlab procedure. This procedure allows optimizing the basic filter parameters - opamp bandwidth, R and C values - in order to satisfy the filter transfer function requirements. Two different design approaches will be considered. The first proposal is based on a 2nd order biquadratic cell. High quality factor is synthesized while guaranteeing the out-of-band frequencies rejection. The second implementation is based on the cascade of two biquadratic cells with more relaxed quality factor requirement. The design is realized using the 90nm CMOS technology. The simulation results for both implementations are presented. The minimum out-of-band rejection is maintained lower than -30dB, the maximum IRN in both cases is 4nV/radicHz and the IM3 is lower than -30dB for two in-band input tones.

In this paper a complete design of an analog 4th order base band filter for WLAN receivers operating at 600mV supply voltage is presented. The design is based on the use of different input and output opamp common mode voltages and on the Input Common Mode Feedback circuit. The ICMFB allows maximizing the overdrive voltages of the opamp input differential pair MOS, guaranteeing the right operating point. The filter is designed using the 0.13μm CMOS technology and features a wide swing performance (DR=68dB@THD=-40dBc when a 800mVpp,differentialsignal is applied at the filter output nodes) and a low power consumption (3.6mW).