While adversarial training is an effective defense method against adversarial attacks, it notably increases the training cost. To this end, fast adversarial training (FAT) is presented for efficient training and has become a hot research topic. However, FAT suffers from catastrophic overfitting, which leads to a performance drop compared with multi-step adversarial training. However, the cause of catastrophic overfitting remains unclear and lacks exploration. In this paper, we present an example taxonomy in FAT, which suggests that catastrophic overfitting is correlated with the imbalance between the inner and outer optimization in FAT. Furthermore, we investigated the impact of varying degrees of training loss, revealing a correlation between training loss and catastrophic overfitting. Based on these observations, we redesign the loss function in FAT with the proposed dynamic label relaxation to concentrate the loss range and reduce the impact of misclassified examples. Meanwhile, we introduce batch momentum initialization to enhance diversity and prevent catastrophic overfitting in an efficient manner. Furthermore, we also propose Catastrophic Overfitting aware Loss Adaptation (COLA), which employs a separate training strategy for examples based on their loss degree. Our proposed method, named example taxonomy aware FAT (ETA), establishes an improved paradigm for FAT. Experiment results demonstrate that our ETA achieves higher robust accuracy than all other evaluated methods. Comprehensive experiments on four standard datasets demonstrate the competitiveness of our method. The source code and model checkpoints will be publicly released.

Adversarial training (AT) is an effective defense method against gradient-based attacks to enhance the robustness of neural networks. Among them, single-step AT has emerged as a hotspot topic due to its simplicity and efficiency, requiring only one gradient propagation in generating adversarial examples. Nonetheless, the problem of catastrophic overfitting (CO) that causes training collapse remains poorly understood, and there exists a gap between the robust accuracy achieved through single- and multi-step AT. In this paper, we present a surprising finding that the taxonomy of adversarial examples reveals the truth of CO. Based on this conclusion, we propose taxonomy driven fast adversarial training (TDAT) which jointly optimizes learning objective, loss function, and initialization method, thereby can be regarded as a new paradigm of single-step AT. Compared with other fast AT methods, TDAT can boost the robustness of neural networks, alleviate the influence of misclassified examples, and prevent CO during the training process while requiring almost no additional computational and memory resources. Our method achieves robust accuracy improvement of 1.59%, 1.62%, 0.71%, and 1.26% on CIFAR-10, CIFAR-100, Tiny ImageNet, and ImageNet-100 datasets, when against projected gradient descent PGD10 attack with perturbation budget 8/255. Furthermore, our proposed method also achieves state-of-the-art robust accuracy against other attacks. Code is available at https://github.com/bookman233/TDAT.

Communication architecture design is a key issue of hardware/software co-design. This paper presents a novel architecture design method, called architecture generation and optimization method (AGOM) to assist embedded system designers to construct optimized on-chip communication architectures (OOCAs). The method outlines a new system design framework to achieve an application-specification architecture exploration process. Under its guide, chip designers can easily synthesize the desired communication structure by the approach of model refinement from one level of abstraction down to another closer to implementation. To automate the key steps of the method, this paper also provides communication synthesis algorithms of architectures generation and optimization based on a pre-partitioned hardware/software specification. During the architecture exploration process, the approach takes into account bus widths, bus load, cost for arbitration logic and transducers to achieve a fine trade-off between system delay and area. The correctness and effectiveness of the method is evaluated through an illustrative JPEG application

The rapidly increasing complexity of integrated circuit design is evolving to a more data-centric design scenario that supports sharing of design information. This paper presents the concepts of universal data model platform (UDMP) which introduce the data-centric design revolution into the domain of system level design to support better cooperation of individual steps in electronic design automation (EDA) industry. The goal of UDMP is to provide a set of universal data models which enables wide variety of codesign tools to be integrated tightly and revitalizes the connection between universities and the EDA industry. Furthermore, an application programming interface (API) takes the place of traditional low-bandwidth file formats to provide access to the internal data models, thus improves efficiency of design iteration. The well-constructed structure of UDMP brings some challenges for the architects as well as current system level researchers and designers. The concepts of UDMP are applied to a simplified interface synthesis flow which contains three algorithms. Primary experiment results show that these algorithms are simplified with a running time reduction by about 10% for selected designs