With the rapid growth of cloud computing services, fully homomorphic encryption (FHE) has attracted much attention because a homomorphic evaluation can be directly performed on ciphertexts to ensure data privacy. This work explores the constraints and an associated minimization algorithm for exclusive sum-of-products (ESOP) expressions based on a homomorphism map and features of FHE. An efficient ESOP minimization algorithm based on the Sierpinski gasket and the triangle rule is proposed to reduce the maximum degree of the ESOP expression, thus relaxing the need to perform the recryption operation on ciphertexts. Experimental results show that about 23% of all candidate 4-variable functions can be further improved by the proposed algorithm to minimize the maximum degree of ESOP as compared with the results obtained using the traditional minimization algorithm.

Power attacks are serious threats to cryptographic devices, and most countermeasures against power attacks result in a large time overhead for hardware implementation. This work presents an efficient countermeasure against power attacks for elliptic curve cryptography over GF(p). The proposed algorithm adopts the Montgomery ladder scalar multiplication algorithm as a basic framework to protect SPA. Then, a new scheme is presented to effectively manipulate the key so as to reduce the resulting time overhead for preventing differential power attack (DPA) and zero power attack (ZPA). Particularly, the base point blinding technique and half key splitting scheme are used to protect the upper and the lower halves of the key, respectively. Experimental results show the proposed countermeasure exhibit a time advantage over related works. Compared to other countermeasures against SPA, DPA, and ZPA, the proposed one can achieve up to 15% time improvement for accomplishing one 160-bit GF(p) scalar multiplication.

Montgomery modular multiplication is widely used in public-key cryptosystems. This work shows how to relax the data dependency in conventional word-based algorithms to maximize the possibility of reusing the current words of variables. With the greatly relaxed data dependency, we then proposed a novel scheduling scheme to alleviate the number of memory access in the developed scalable architecture. Analytical results show that the memory bandwidth requirement of the proposed scalable architecture is almost $(1/(w-1))$ times that of conventional scalable architectures, where $(w)$ denotes word size. The proposed one also retains a latency of exactly one cycle between the operations of the same words in two consecutive iterations of the Montgomery modular multiplication algorithm when employing enough processing elements. Compared to the design in the related work, experimental results demonstrate that the proposed one achieves an almost 54 percent reduction in power consumption with no degradation in throughput. The reduced number of memory access not only leads to lower power consumption, but also facilitates the design of scalable architectures for any precision of operands.

This work presents a look-up table-based (LUT-based) algorithm for scanline-based rendering of OpenVG. The proposed method can deal with arbitrary number of scissoring rectangles. The rasterization and scissoring in the proposed architecture can be performed concurrently to reduce rendering time. The scanline-size buffers used as scissoring LUTs result in low area overhead. Moreover, a linked list structure of scissoring rectangles is proposed in order that only the scissoring rectangles interacted with the processing scanline are accessed to increase bus efficiency and reduce power consumption. Implementation results based on TSMC 0.13-μm CMOS technology show that the proposed rasterization design with LUT-based scissoring can operate at 200 MHz with 77K gate counts. The proposed design can render 16.8 tiger images with 392×483 resolution per second assuming ideal bus latency. Compared to existing works, the proposed design achieves a smaller area and more functionality for higher display resolution with comparable throughput.

Montgomery modular multiplication is widely applied to public key cryptosystems like Rivest-Sharmir-Adleman (RSA) and elliptic curve cryptography (ECC). This work presents a word-based Booth encoded radix-4 Montgomery modular multiplication algorithm for low-latency scalable architecture. The data dependency resulting from the inherent right shifting of the intermediate results in the conventional radix-4 Montgomery modular multiplication algorithm is alleviated; thus the latency between the neighboring process elements (PEs) is exactly one cycle. The number of the equivalent operands in the accumulation is not increased with operand reduction scheme. Implementation results based on the same technology show that compared to other Booth encoded radix-4 Montgomery modular multipliers, the proposed design achieves at least 23% time reduction for accomplishing one 1024-bit Montgomery modular multiplication.

Embedded processors are ubiquitous in today's system-on-chip design. In addition to designing digital signal processors (DSPs) for various applications, developing efficient test methods with little overhead and desired fault coverage for DSPs are also crucial and practical. Compared with the scan-based test methods, the software-based self-test (SBST) method does not suffer from area overhead and performance degradation, and can provide at-speed test for DSPs with the potential drawbacks of lower fault coverage and a larger amount of test vectors. This paper explores techniques to improve the fault coverage of SBST methods for the developed DSP core with instructions fully compatible with those of the TI TMS320C54x. Experimental results exhibit that applying the developed SBST test flow obtains more than 96% fault coverage for our DSP core, which is higher than the reported values in related works.