Electromigration (EM) is crucial for interconnect reliability. This article introduces the implementation and application of CacheEM which targets SRAM cache memory aging due to EM. CacheEM is based on a comprehensive framework including five parts: 1) microprocessor emulation; 2) memory cell array activity extraction; 3) computation of currents in segments of long complex interconnect structures; 4) evaluation of the time-dependent hydrostatic stress and the resistance shift of interconnects; and 5) characterization of the EM lifetime distribution of interconnects in the cache memory. The first two steps (top-down) are implemented with gem5 and cache simulation, respectively. These simulators export the number of read and write operations for each cell of a cache memory in a microprocessor after running benchmarks. Then, based on the number of operations and the currents corresponding to each operation, CacheEM calculates the equivalent current distribution in each interconnect segment as the third step (bottom-up). The currents due to read and write operations are stored in models which have been pretrained with a regression algorithm. These models provide accurate predictions of the corresponding currents under various parameter settings, such as temperature, supply voltage, and gate length. Afterward, the samples of time-dependent hydrostatic stress and the resistance shift in each interconnect segment are computed while incorporating the variations of the effective activation energy and critical stress. The EM lifetime distribution of the cache memory is extracted using predefined threshold values. The impact of configuration parameters on EM reliability and performance of the SRAM cache is analyzed by comparing EM lifetime distributions.

This article describes a comprehensive framework for analysis of time-dependent performance-reliability degradation of an SRAM cache, considering cache configurations, process parameters and their variations, supply voltage, and aging. The framework consists of three parts: microprocessor emulation, activity extraction, and evaluation of performance-reliability metrics. Evaluation of performance-reliability metrics is implemented with a prediction engine involving regression models for the metrics, which evaluates degradation due to various wearout mechanisms, including bias temperature instability (BTI), hot carrier injection (HCI), and random telegraph noise (RTN). The regression models not only enable more than 100× faster computation compared with SPICE simulations but also protect intellectual property. This framework has been applied to study how SRAM instruction cache (I-Cache) configurations, cell structure, inclusion of RTN and gate length variation, voltage scaling, and stress time affect the performance and reliability parameters, such as access time, leakage power, critical charge ( Qcrit), and static noise margin (SNM). We have also studied the impact of configuration parameters on the soft error rate (SER) and the hit rate of the I-Cache, and the impact of single error correction and double error detection (SECDED) error correcting codes (ECCs).

A framework is presented to identify an optimal accelerated test region and accelerated test conditions for the accelerated test of logic circuits for time-dependent dielectric breakdown (TDDB). Both gate-oxide breakdown and middle-of-line (MOL) TDDB are investigated. Separate test regions are identified for each wearout mechanism. Two digital circuits, an 8-bit fast Fourier transform (FFT) circuit and a Leon3 microprocessor are used to demonstrate the capability of the framework. The lifetimes of standard cells are combined to compute the circuit lifetime, by combining the Weibull distributions that characterize the lifetime distribution of each of the standard cells. The errors in estimating wearout parameters consist of two parts: the error in estimating the wearout parameters at accelerated test conditions and the forecasting accuracy at use conditions. By estimating the errors in wearout parameters at accelerated test conditions, the optimal accelerated test region is found by determining the test conditions producing a minimal error. Test conditions are selected by minimizing the error at use conditions. Given a forecasting error target, the required sample size at each test condition is found. This work also considers the impact of variation in circuit size, type, and process parameters on the selection of optimal test conditions.

Bias temperature instability (BTI), hot carrier injection (HCI), gate-oxide time-dependent dielectric breakdown (GTDDB), and random telegraph noise (RTN) degrade the stability of the deeply scaled transistors and the overall circuit reliability. These front-end wearout mechanisms are especially acute in the static random access memory (SRAM) cells of first-level (L1) caches, which are crucial for the performance of microprocessors due to frequent accesses. This article presents a methodology to analyze cache reliability degradation due to the combined effect of BTI, HCI, GTDDB, and RTN for different cache configurations, including variations due to associativity, cache line size, cache size, and the error-correcting codes (ECCs). Time-zero variability due to process and environmental parameters are also considered. First, we analyze how each wearout mechanism affects reliability degradation. Then we analyze the relationship between reliability (probability of failure) and performance (hit rate) of the L1 cache within a LEON3 microprocessor, while the LEON3 is running a set of benchmarks, which determine cell array activity, characterized by the duty cycle, toggle rate, temperature, and supply voltage distributions of cells. Insights on the performance-reliability tradeoff are provided for cache designers.

Circuits may fail in the field due to a wide variety of failure modes. If there are frequent failures in the field, circuits are returned to the manufacturer, and the causes of failure must be identified. The challenge is that wearout mechanisms are confounded in circuit and system-level failure data. Using such failure data, it is often hard to separate the underlying failure causes without time-consuming and expensive physical failure analysis. To distinguish the wearout mechanisms for each failure sample, we have developed a quick and low-cost methodology using maximum likelihood estimation and probability analysis to determine the origin of the failure distributions, region of error, and sorting accuracy. We apply our methodology to analyze the competing wearout mechanisms in 14nm FinFET ring oscillators, as an example, using simulation. We also consider the problem of Trojan detection.

This paper presents a lifetime simulator for both Front-End-of-Line (FEOL) time dependent dielectric breakdown (TDDB) and the newly emerging Middle-of-Line (MOL) time dependent dielectric breakdown for FinFET technology. A lifetime assessment flow for digital circuits and microprocessors is proposed for the target wearout mechanisms, and its associated vulnerable feature extraction algorithms are discussed in detail. Our simulator incorporates the detailed electrical stress, temperature, linewidth of each standard cell within the digital circuit and microprocessor. Also, FEOL TDDB and MOL TDDB lifetimes are combined in the calculation of TDDB lifetime. Circuit designers can use the resulting lifetime information to guide and improve their circuits to make them more robust and reliable.