In integrated Digital-to-Analog Converters (DACs), random mismatch errors among nominally equal unit elements significantly limit the achievable accuracy. This work explores the effectiveness of tailored Dynamic Element Matching (DEM) techniques in mitigating mismatch-induced non-linearity errors in resistor-string DAC architectures. Through statistical behavioural simulations, we identify effective DEM strategies that substantially reduce Integral Non-Linearity (INL). The proposed technique enables virtually zero INL errors at specific points of the transfer characteristic, which can be strategically chosen during circuit operation. Insofar, optimized design approaches for resistor-string DACs are proposed, fostering future integratedcircuit implementations with superior yield concerning accuracy and linearity specifications.

Thanks to their simplicity and scalability, R-2R DACs find widespread employment in present-day applications of integrated circuits, including miniaturized sensing devices and other emerging contexts. However, they typically yield limited accuracy due to mismatch errors. To tackle this issue, two dynamic element matching (DEM) techniques, customized for R-2R DACs, are herein proposed, trading off operating frequency with accuracy. Statistical behavioural simulations have been performed to compare the presented approaches, highlighting comparable performances, with reductions of the standard deviation of INL down to a factor of 0.26. Thereby, design guidelines for optimized DEM-compensated R-2R DACs are suggested.

Driven by the ongoing challenge of designing high-accuracy digital-to-analog converters (DACs) at the cost of a relatively small area occupation, optimal combination algorithms (OCAs) recently gained attention within the myriad of possible calibration techniques for DACs. OCAs show appealing properties with respect to traditional approaches such as dynamic element matching (DEM). At start-up or upon request, mismatches affecting DAC elements are measured on-chip, allowing rearrangement in the selection logic of the DAC unit elements. The newly found arrangement is, hence, used during normal operation, achieving superior linearity. As of today, several alternative OCAs have been proposed; however, designers willing to implement OCA-calibrated DACs are faced with unclear tradeoffs and insufficient design guidelines. In this work, we provide a detailed comparison of existing OCAs based on statistical behavioral simulations. Starting from this, we investigate the relationships between OCAs’ performances and circuit-level design aspects. Specifically, OCAs’ effectiveness in improving the static linearity is linked to the number of DAC bits and the accuracy of the auxiliary comparator required by every OCA. Unforeseen trends emerge, and new design considerations are suggested, fostering novel awareness on the subject of high-accuracy DAC designs enabled by OCA-based calibration techniques.

This paper presents a 0.8-mW 0.2-mm29-level second-order single-loop SC Delta-Sigma modulator (ΔM) ADC in 1.8-V 0.18-μm CMOS technology for low-power high-resolution sensing applications. The ΔM circuit features 94.6-dB peak SNDR in 50-kHz bandwidth and 103.5 dB SFDR up to -1 dBFSinput for 2-Vpp differential full scale. The proposed built-in CDS flicker noise cancellation allows a net improvement of 10 dB FOMS. The bootstrapping-free CMOS circuits incorporate variable-mirror Class-AB switched OpAmps and a 10μW resistor-less flash quantizer. The obtained 172.6-dB FOMSis competitive within the state-of-art high-resolution (SNDR > 90 dB) and generalpurpose (bandwidth > 20 kHz) SC ASM ADCs.

This paper presents a potentiostatic-amperometric Delta-Sigma modulator (ΔΣM) for electrochemical sensors, which reuses the electrode-electrolyte impedance for quantization noise shaping. The proposed ΔΣM is based on a second-order single-bit CT architecture and it includes a cancellation mechanism of the flicker noise coming from the feedback DAC. Rail-to-rail CMOS basic building blocks for the ΔΣM circuit implementation are presented with the aim of allowing a wide-range potentiostatic operation. Post-layout simulation results are reported for a complete 72-μW 90-dB smart electrochemical sensor frontend currently being integrated in 0.18-μm 6-metal CMOS technology.

This paper presents a novel frequency-domain multiplexing scheme of liquid-gate GFET sensors for large-scale μECoG recording. The proposed technique allows the hybrid integration of GFET arrays and read-out ICs. In order to avoid artifacts, the proposal does not employ any switch in the GFET array and it is insensitive to the flicker noise of the CMOS frontend. A modular read-out IC architecture targeting the continuous acquisition of up to 1024 μECoG channels is introduced together with a collection of low-power CMOS circuits for the practical implementation of each building block. A test chip of the proposed system is currently being integrated in 0.18-μm 6-metal CMOS technology.

This paper proposes a compact switched-capacitor (SC) multi-bit flash quantizer for low-power high-resolution delta-sigma modulators (ΔΣMs). First, a general power model for single-loop ΔΣMs is presented to show the importance of using multi-bit quantization when facing high-resolution specifications. In this context, a SC multi-bit quantizer circuit is proposed, which exhibits low-power operation, high modularity, single comparator design and compatibility with both multi-feedforward ΔΣM architectures and other SC low-power circuit techniques, like clocked comparators and switched OpAmps. A practical 50-kHz 16-bit ΔΣM design case is also presented.

This paper presents a complete family of integrate- and-fire modulator (IAF) topologies to improve in-pixel signal linearity in digital imagers. Three types of soft-reset schemes are analyzed for capacitive trans-impedance amplifiers (CTIAs). The proposed Type III has the main advantages of avoiding any low-impedance voltage source or extra capacitor, of including correlated double sampling (CDS) for the cancellation of CTIA low-frequency noise, and of minimum current biasing requirements. Comparative electrical simulations are also presented to demonstrate the linearity improvements of soft-reset schemes and the increase of IAF modulation robustness under low-power circuit operation.

This paper presents a highly linear current-controlled ring-oscillator (CCRO) circuit for current-to-frequency ADC in smart sensing. The proposed CCRO topology employs a distributed regulation of the oscillator rail voltage for lowering its sensitivity with respect to the controlling input current. The use of a current conveyor for this purpose ensures the stability of the current-steering control loop together with low-area and low-power overheads. A practical circuit design example is supplied in 0.18-μm 1P6M CMOS technology consisting on a 10-bit 100-kS/s ADC without the need of any digital calibration nor postcompensation technique.

This paper presents a 96.6-dB-peak-SNDR and 50-kHz-bandwidth switched-capacitor delta-sigma modulator for ADC operating at 1.8 V and consuming 7.9 mW. This performance is achieved by the introduction of Class-AB single-stage switched variable-mirror amplifiers (VMAs) combined with an optimized architecture and a 5-phase switched-capacitor scheme. The resulting 1.8-mm2delta-sigma modulator is integrated in a standard 0.18-μm 1P6M CMOS technology and reaches a Schreier figure of merit of 164.6 dB from experimental SNDR measurements without the need for any clock bootstrapping, analog calibration or digital compensation technique.

This paper presents a new family of Class-AB operational amplifier (OpAmp) circuits based on single-stage topologies with nonlinear current amplifiers. The proposed OpAmp architecture is mainly characterized by generating all Class-AB current in the output transistors only, exhibiting very low technology sensitivity and avoiding the need of any internal frequency compensation mechanism. Hence, this family of OpAmps are suitable for low-power switched-capacitor circuits and specifically optimized for switched-OpAmp fast on-off operation and multi-decade load capacitance specifications. A complete OpAmp design example integrated in standard 0.18μm 1P6M CMOS technology is supplied with detailed simulation and experimental results. Compared to MOS-only state-of-art Class-AB OpAmp literature, the proposed architecture returns the highest figure-of-merit value.

This paper presents a novel digital pixel architecture for MWIR PbSe sensors and high-speed AER imagers. Low-power and compact circuits are proposed for pixel built-in log-domain temporal contrast, signal adapted self-biasing, linear current to spike frequency conversion under high-speed AER communications, and digital PLL-based technology and temperature compensated tuning. The proposed CMOS design techniques make extensive use of transistor subthreshold operation and circuit reuse. The resulting 40μm-pitch digital pixel is designed in standard 0.35μm 2P4M CMOS technology, and preliminary simulation results are reported.