A 12.5-Gb/s 1/5-rate reference-less subsampling clock and data recovery (CDR) circuit is presented. The subsampling phase detection technique widely used in the low jitter phase-locked loop design is adopted for the CDR’s clock recovery operation. It brings not only a design simplification but also the low-power consumption of the CDR. The 1/5-rate subsampling phase detection circuit is also introduced for further power reduction. The false-lock detector is proposed that monotonically ascends or descends the clock frequency until the phase lock is achieved. It shares the outputs of the subsampling phase detection circuit and removes the frequency detector from the CDR loop. The measured power consumption and efficiency of the proposed CDR at 12.5 Gb/s are 8.8 mW and 0.7 pJ/bit, respectively. At the same time, the peak-to-peak and rms jitters show 21 and 3.7 ps in 2.5-GHz clock signal, respectively. The high-frequency jitter tolerance is 0.52 UIpp. The CDR including a 1-to-5 DEMUX occupies a core area of 0.087 mm2 using 65-nm CMOS process.

This article presents an receiver (RX) only equalization (ROE) technique that eliminates feed-forward equalization (FFE) in transmitter (TX) and bandwidth improved output driver without increment of power consumption. With a help of the proposed design technique, the power consumption, circuit complexity, and design cost are improved. The proposed RX with one-tap finite-impulse response (FIR) and second-tap IIR decision feedback equalizer (DFE) removes the FFE equalization in TX by moving the sampling point of main cursor in the received data. A simpler TX architecture with nMOS only output driver (NOD) owing to the ROE facilitates a wide bandwidth and energy efficient dual-mode (differential and single-ended) operation. The proposed transceiver was fabricated in a 65-nm CMOS technology. The RX achieves bit error rate (BER) less than 10^{-12} over a 22-dB channel loss at 32 Gb/s with 0.62-pJ/bit energy efficiency, and the TX with NOD has 0.77- and 0.40-pJ/bit energy efficiency at 32 Gb/s in differential mode and single-ended mode, respectively. The occupied area of TX and RX is 0.002 and 0.024 mm2, respectively.

A 10 Gbits/s/pin graphics DRAM interface is developed in 65-nm CMOS technology. Several design techniques are proposed for high-speed operation in a noisy environment. A fast precharging data sampler guarantees high-speed sampling without the need for a decision feedback equalizer. In order to increase the data sampling margin, the PLL bandwidth is optimized depending on the system noises, which reduces the clock jitter by up to 55.1%. The crosstalk-induced jitter (CIJ) reduction technique suppresses the DQs jitter by employing the suggested training sequence for the GDDR5 interface. Pre- and de-emphasis are merged in one auxiliary driver. This chip operates at 10 Gbits/s/pin and exhibits a data eye opening of 0.78 UI with the CIJ reduction technique. The power consumptions of the TX and RX are 8.28 and 5.5 pJ/b/channel, respectively.

An add-on type real-time jitter tolerance enhancer (JTE) is presented in this paper. The proposed JTE can improve high-frequency jitter tolerance (JTOL) by using a real-time phase alignment scheme. A mathematical analysis for an advanced bit error rate (BER) prediction method is also introduced. The proposed circuit is applicable to various types of receivers, such as referenceless receivers, receivers with a reference clock source, and source-synchronous receivers. The referenceless receiver with the proposed JTE achieved an out-of-band JTOL of 0.71 UIppat 100 MHz with-12BER. This is 196% higher than a conventional receiver without the JTE. The source-synchronous receiver with the proposed JTE achieved 0.92 UIpp at 300 MHz with-12BER. Total core areas of the receiver and JTE are 0.19 and 0.07 mm2in a 0.13-μm CMOS process, respectively. The power consumption of the receiver is 38 mW at 5.4 Gbit/s, and the JTE dissipates 22 mW.

A 4×5-Gb/s reference-less receiver is proposed in a 0.13-μm CMOS technology. In the proposed reference-less clock and data recovery (CDR) circuit, asynchronous sampling-based frequency acquisition is proposed to achieve a fast frequency locking, and VCO calibration is proposed to attain a constant loop bandwidth. To reduce noise caused by multiple VCOs, a clock signal is forwarded from the main channel to the subchannels, and skews between the channels are compensated by a skew compensation algorithm. In the main channel, the reference-less CDR achieves a 1.12-μs locking time, and the measured standard deviation of VCO gain is reduced from 0.33 to 0.08. The recovered clock jitter in the main channel is 1.591 psrms, and the power consumption of the main channel and the subchannels are 3.53 and 2.16 mW/Gb/s, respectively.

Cameras and image sensors have recently been installed in many portable devices. An image processor and a transceiver are also adopted in multimedia system-on-a-chip to handle the data from the image sensor. A wide input range and flexible data bandwidth are needed for the serial link receiver to deal with various sensor specifications. This paper presents an 11.2-Gb/s low-voltage differential signaling (LVDS) receiver for various portable devices that employ a LVDS system for data transmission between an image sensor and a processor. The designed LVDS receiver has 16 data channels and four clock channels. All the channels are selectively turned on or off, depending on the application. The proposed comparator used for the input driver of the receiver has a rail-to-rail input range and 60 mV of minimum input swing level. The clock dividing ratio and the data de-serializing factor of the proposed receiver are also programmable to deal with various color depths of image sensors. The designed LVDS receiver is fabricated in a 0.13-μm CMOS process, occupying 4-4 mm, with a 7.24-mm2core. Power consumption is 77.38 mW, when every channel is turned on.

A 7.5Gb/s referenceless transceiver for the ultra-high definition television is designed in a 0.13μm CMOS process. By applying the dynamic pre-emphasis calibration and the bandwidth scanning clock generators, measured eye opening and jitter of the clock are enhanced by 39.6% and 40%, respectively. Also the data-width comparison based adaptive equalizer with self-adjusting reference voltage is proposed.

This paper presents the silicon-proven design of a novel on-chip network to support guaranteed traffic permutation in multiprocessor system-on-chip applications. The proposed network employs a pipelined circuit-switching approach combined with a dynamic path-setup scheme under a multistage network topology. The dynamic path-setup scheme enables runtime path arrangement for arbitrary traffic permutations. The circuit-switching approach offers a guarantee of permuted data and its compact overhead enables the benefit of stacking multiple networks. A 0.13-μ m CMOS test-chip validates the feasibility and efficiency of the proposed design. Experimental results show that the proposed on-chip network achieves 1.9× to 8.2× reduction of silicon overhead compared to other design approaches.

An adaptive equalizer that operates at 5.4Gb/s with unit pulse charging technique is introduced in this paper. The proposed method has a simple architecture with compensating the channel adaptively. The common mode detection of the equalizer filter output with the resister ladder that can generate the reference voltages depending on the common level of the output of the filter is presented as well. The eye opening of the equalizer at 5.4Gb/s is 0.61UI with a 2m DisplayPort cable, and the BER is less than 10-12at the same conditions. The power consumption is 17.64mW, and our equalizer occupies a core area of 0.069mm2using 0.13μm CMOS process.