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Chiu-Cheng Hsieh

dblp:55/10660 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 2014
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Graphics, computer vision, multimedia, augmented reality and games · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
GPUs and heterogeneous computing · 50% Energy-efficient computing · 50%
Computer graphics and multimedia
1 paper
Rendering · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
GPUs and heterogeneous computing › GPU scheduling
GPU thread scheduling
0.212014
An Adaptive Thread Scheduling Mechanism With Low-Power Register File for Mobile GPUs · IEEE Trans. Multim. 2014
GPUs and heterogeneous computing › embedded GPU
mobile GPU
0.212014
An Adaptive Thread Scheduling Mechanism With Low-Power Register File for Mobile GPUs · IEEE Trans. Multim. 2014
Energy-efficient computing
power management
0.212014
An Adaptive Thread Scheduling Mechanism With Low-Power Register File for Mobile GPUs · IEEE Trans. Multim. 2014
Energy-efficient computing › memory energy efficiency
register file energy reduction
0.212014
An Adaptive Thread Scheduling Mechanism With Low-Power Register File for Mobile GPUs · IEEE Trans. Multim. 2014
Rendering
real-time rendering
0.112014
An Adaptive Thread Scheduling Mechanism With Low-Power Register File for Mobile GPUs · IEEE Trans. Multim. 2014

Methods — techniques the papers use, named apart from their topics

multiple power modes · 0.4adaptive thread scheduling · 0.4
YearPublicationVenuePosition
2014 An Adaptive Thread Scheduling Mechanism With Low-Power Register File for Mobile GPUs
abstract
In response to the remarkable increase in 3D applications in consumer electronics devices in recent years, graphics processing units (GPUs) have become widely available on mobile devices. These GPUs typically use hardware multithreaded shaders to improve their throughputs for real-time rendering, but they depend on duplicate register files to maintain the context of each hardware thread, increasing power consumption. However, the register usage of shading programs is often relatively low, which causes many registers to remain unused, thus wasting power. Long latency memory operations can also consume unnecessary power to activate registers. This study proposes a low-power register file with multiple power modes to reduce the power consumption of the register file. This study also presents an adaptive thread scheduling mechanism to achieve a tradeoff between the power consumption of the register file and frames per second (FPS). Results show that the average performance degradation from the proposed low-power register file is only 0.62%. The proposed adaptive thread scheduling has average under prediction ratio of 3.32%. The leakage reduction of the proposed low-power register file is 74.80%. This reduction can be improved to 81.49%, 82.22%, and 84.28% with adaptive thread scheduling at frame rates of 30, 25, and 20, respectively.
Chih-Chieh Hsiao, Slo-Li Chu, Chiu-Cheng Hsieh
IEEE Trans. Multim.3
2011 An Energy-Efficient Unified Register File for Mobile GPUs
abstract
The programmability of mobile GPUs have raised in recently years, where the shaders inside are instructed by shading programs for realistic 3D effects. The register files for a conventional high throughput multithreaded shader consumes 10% to 20% energy of it. However the register usages of shading program are quite low. In order to reduce the dynamic energy for register file in a multithreaded mobile shader, this paper proposed an unified register file design to reduce both dynamic and leakage energy of it. The result shows that proposed design reduces 85% of dynamic energy in a multithreaded register file. Furthermore, the proposed design reduces 59% of leakage energy and 25% of area with negligible performance degradation. Also, the energy savings in proposed designs are at least 75% more than related work.
Slo-Li Chu, Chih-Chieh Hsiao, Chiu-Cheng Hsieh
EUC3