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Demo Data from EDBT 2026 / reviewers in the wild / expert

R. Ramnarayan

dblp:55/10969 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1984
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 87% Integrated circuit design · 13%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design › design planning
chip planning		 0.011984
Spider, a chip planner for ISL technology · DAC 1984
Electronic design automation
physical design		 0.011984
Spider, a chip planner for ISL technology · DAC 1984
YearPublicationVenuePosition
1984 Spider, a chip planner for ISL technology
Prakash Rao, R. Ramnarayan, Gerhard Zimmermann
 DAC2