Demo Data from EDBT 2026 / reviewers in the wild / expert
Sanjay Patel
dblp:55/1828
· DBLP profile ↗
11ranked-venue papers
1as first author
0since 2021 · last 2013
0000-0001-9540-9957ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 9 · 1 first-authorHuman-computer interaction and ubiquitous computing · 1Applied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Electronic design automation · 100% |
Topics — the 8 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test › design for testability
built-in self-test |
0.1 | 3 | 2004 | Scalable selector architecture for x-tolerant deterministic BIST · DAC 2004 Efficient compression and application of deterministic patterns in a logic BIST architecture · DAC 2003 Effective diagnostics through interval unloads in a BIST environment · DAC 2002 |
Electronic design automation
hardware verification and test |
0.1 | 3 | 2004 | Scalable selector architecture for x-tolerant deterministic BIST · DAC 2004 Efficient compression and application of deterministic patterns in a logic BIST architecture · DAC 2003 Effective diagnostics through interval unloads in a BIST environment · DAC 2002 |
Electronic design automation › hardware verification and test
test data compression |
0.1 | 2 | 2004 | Efficient compression and application of deterministic patterns in a logic BIST architecture · DAC 2003 Scalable selector architecture for x-tolerant deterministic BIST · DAC 2004 |
Electronic design automation › hardware verification and test › design for testability
scan-based testing |
0.0 | 1 | 2004 | Scalable selector architecture for x-tolerant deterministic BIST · DAC 2004 |
Electronic design automation › hardware verification and test › design for testability
scan chain design |
0.0 | 1 | 2004 | Scalable selector architecture for x-tolerant deterministic BIST · DAC 2004 |
Electronic design automation › hardware verification and test › design for testability › built-in self-test
logic BIST |
0.0 | 1 | 2003 | Efficient compression and application of deterministic patterns in a logic BIST architecture · DAC 2003 |
Electronic design automation › hardware verification and test › design for testability › built-in self-test
BIST diagnosis |
0.0 | 1 | 2002 | Effective diagnostics through interval unloads in a BIST environment · DAC 2002 |
Electronic design automation › hardware verification and test
fault diagnosis |
0.0 | 1 | 2002 | Effective diagnostics through interval unloads in a BIST environment · DAC 2002 |
Methods — techniques the papers use, named apart from their topics
ATPG · 0.1LFSR seeding · 0.0interval-based scan unload · 0.0STIL · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2013 | Rule based regression and feature selection for biological dataabstractRegression is widely utilized in a variety of biological problems involving continuous outcomes. There are a number of methods for building regression models ranging from linear models to more complex nonlinear ones. While linear regression techniques can identify linear correlations between input and output, in many practical applications, the relations are nonlinear. These relations can be modeled by nonlinear regression techniques effectively. However, many models built with nonlinear techniques have limited interpretation, which is crucial in many biological problems. We propose a rule based regression algorithm that uses 1-norm regularized random forests. The proposed approach simultaneously extracts a small number of rules from generated random forests and eliminates unimportant features, and hence is able to provide a simple interpretation. We tested the approach on a seacoast chemical sensors dataset, a Stockori flowering time dataset, and three datasets from the UCI repository. The proposed approach is able to construct a significantly smaller set of regression rules using a subset of attributes while achieving prediction performance comparable to that of conventional random forests regression. It demonstrates high potential in terms of prediction performance and interpretation ease on studying nonlinear relationships of the subjects. Shamitha Dissanayake, Sanjay Patel, Xin Dang, Todd Mlsna, Yixin Chen 0002, Dawn Wilkins |
BIBM | 3 |
| 2009 | Rainbow falls sun's next generation CMT processor
Sanjay Patel |
Hot Chips Symposium | 1 |
| 2007 | Automated Design and Insertion of Optimal One-Hot Bus EncodersabstractTristate buses, commonly used in high-performance designs, raise testability problems because one-hot conditions, required for functional operation, may not be maintained during scan testing. We present a novel method to automatically generate and insert a bus encoder that ensures one-hot bus operation. Each bus is analyzed individually; a customized encoder is then generated and optimized for best testability and minimal area and delay. We introduce two new bus encoder designs which form the basis of a hierarchically algorithm that scales up to any number of bus inputs. Peter Wohl, John A. Waicukauski, Sanjay Patel |
VTS | 3 |
| 2006 | AdapTex: contextually adaptive text entry for mobilesabstractThis demonstration introduces AdapTex: a new text entry system that suggests words and phrases to the user based on the current working context on the device, the user's history on the device and an initial corpus analysis. User studies show that AdapTex speeds up text entry while reducing errors. Mark D. Dunlop, Andrew Glen, Sunil Motaparti, Sanjay Patel |
Mobile HCI | 4 |
| 2005 | Efficient compression of deterministic patterns into multiple PRPG seedsabstractRecent test-cost reduction methods are based on controlling the initial state (seed) of a pseudo-random pattern generator (PRPG) so that deterministic values are loaded in selected scan cells. Combined with an unload-data compression technique, PRPG seeding reduces test data volume and application time. This paper presents a method of mapping each scan load to multiple PRPG seeds, computed so that test pattern count, data volume, and, therefore, test cost are minimized. This method also allows smaller and fewer PRPGs, reducing the area overhead of test-compression circuitry. The results on deep-submicron industrial designs, show significant test cost reduction when this method is applied with either X-tolerant or X-free unload-data compression Peter Wohl, John A. Waicukauski, Sanjay Patel, Francisco DaSilva, Thomas W. Williams, Rohit Kapur |
ITC | 3 |
| 2005 | Hierarchical Compactor Design for Diagnosis in Deterministic Logic BISTabstractScan-based tests created by automatic test pattern generators (ATPG) can be efficiently compressed and applied in a deterministic built-in self-test (DBIST) architecture. However, the BIST environment adds significant complexity to failure diagnosis. We present a simple scan-compatible diagnosis solution - streaming DBIST (SDBIST), which is based on a low-overhead hierarchical compactor SDBIST allows continuously monitoring streaming scanout data for reduced-volume expect-data diagnosis, on-line fail-data collection and selective scan cell masking. Peter Wohl, John A. Waicukauski, Sanjay Patel, Cy Hay, Emil Gizdarski, Ben Mathew |
VTS | 3 |
| 2004 | Scalable selector architecture for x-tolerant deterministic BISTabstractX-tolerant deterministic BIST (XDBIST) was recently presented as a method to efficiently compress and apply scan patterns generated by automatic test pattern generation (ATPG) in a logic built-in self-test architecture. In this paper we introduce a novel selector architecture that allows arbitrary compression ratios, scales to any number of scan chains and minimizes area overhead. XDBIST test-coverage, full X-tolerance and scan-based diagnosis ability are preserved and are the same as deterministic scan-ATPG. Peter Wohl, John A. Waicukauski, Sanjay Patel |
DAC | 3 |
| 2004 | Hierarchical Storage Management at the NASA Center for Computational Sciences: From Unitree to SAM-QFS
Ellen Salmon, Adina Tarshish, Nancy Palm, Sanjay Patel, Marty Saletta, Ed Vanderlan, Mike Rouch, Lisa Burns, Daniel C. Duffy, Robert Caine, Randall Golay, Jeff Paffel, Nathan Schumann |
MSST | 4 |
| 2003 | Efficient compression and application of deterministic patterns in a logic BIST architectureabstractWe present a novel method to efficiently generate, compress and apply test patterns in a logic BIST architecture. Patterns are generated by a modified automatic test pattern generator (ATPG) and are encoded as linear feedback shift register (LFSR) initial values (seeds); one or more patterns can be encoded into a single LFSR seed. During test application, seeds are loaded into the LFSR with no cycle overhead. The method presented achieves reductions of at least 100x in test data and 10x in tester cycles compared to deterministic ATPG while maintaining complete fault coverage, as confirmed by experimental results on industrial designs. Peter Wohl, John A. Waicukauski, Sanjay Patel, Minesh B. Amin |
DAC | 3 |
| 2003 | X-Tolerant Compression And Application of Scan-ATPG Patterns In A BIST Architecture
Peter Wohl, John A. Waicukauski, Sanjay Patel, Minesh B. Amin |
ITC | 3 |
| 2002 | Effective diagnostics through interval unloads in a BIST environmentabstractLogic built-in self test (BIST) is increasingly being adopted to improve test quality and reduce test costs for rapidly growing designs. Compared to deterministic automated test pattern generation (ATPG), BIST presents inherent fault diagnostic challenges. Previous diagnostic techniques have been limited in their diagnosis resolution and/or require significant hardware overhead. This paper proposes an interval-based scan-unload method that ensures diagnosis resolution down to gate-level faults with minimal hardware overhead. Tester fail-data collection is based on a novel construct incorporated into the design-extensions of the standard test-interface language (STIL). The implementation of the proposed method is presented and analyzed. Peter Wohl, John A. Waicukauski, Sanjay Patel, Gregory A. Maston |
DAC | 3 |