In the advanced process technologies of 7nm and beyond, the semiconductor industry faces several new challenges: (1) aggressive chip area scaling with economically feasible process technology development, (2) sufficient performance enhancement of advanced small-scale technology with significantly increased wire and via resistances, (3) power density sustainability with ever shrinking chip area, and (4) advanced chip packaging integration solutions for complex SOC systems. In this presentation, novel physical design solutions of robust IP and design methodologies will be explored to solve these challenges. These innovations are made possible by the co-optimization of process technology, IP design and design flow automation. Density scaling is the most important indicator in the continuation of Moore's law. Before 10nm, chip area reduction is mainly achieved by fundamentally shrinking transistor and metal dimensions. Starting from 7nm, maintaining sufficient and economical scaling is hard to achieve through dimension decrease alone. We present two cost-effective enablers, FIN depopulation and EUV, along with their associated innovative standard cell structures and physical design flows, to realize additional area reduction beyond process dimension scaling.

This paper presents a formal mathematical framework which unifies the existing loop transformations.This framework also includes more general classes of loop transformations, which can extract more parallelism from a class of programs than the existing techniques.We classify schedules into three classes: unij'orm, subdomainvariant, and statement-variant.Viewing from the degree of parallelism to be gained by loop transformation, the schedules can also be classified as single-sequential level, multiple-sequential level, and mited schedules.We also illustrate the usefulness of the more general loop transformation with an example program.

The authors present a new dependence test which can detect disjoint regions of an iteration space. The test therefore reports accurate dependences for a class of conditional statements. The proposed algorithm can discover large-scale parallelism in cases where previous decision algorithms fail. The methods and algorithms for solving the subdomain dependence test are described. Also considered is the application of the subdomain dependence test to the problem of 'dependence cycle breaking' and the use of the subdomain dependence test in analyzing functional programs.>