A 21.6–37.1 GHz broadband low-noise amplifier (LNA) is presented, featuring a magnetically coupled resonator (MCR) at the output stage for inherent bandwidth extension and output matching. To overcome the limitation of the MCR, which tunes only one pole, an additional coupling inductor is introduced to adjust the second pole via its coupling coefficient, enabling flexible dual-pole bandwidth extension while maintaining gain flatness. The LNA is implemented in 130-nm SiGe BiCMOS technology with a core area of$0.128~\text {mm}^{2}$. It achieves a peak gain of 21.5 dB across a 3-dB bandwidth of 21.6–37.1 GHz, with a gain ripple of 1.5 dB. The measured noise figure ranges from 1.9 to 2.6 dB, and the input 1-dB compression point ($\text {IP}_{\text {1dB}}$) remains stable between −23.5 and −21.5 dBm across the entire bandwidth. The LNA consumes 14.5 mW from a 1.2 V supply, demonstrating a compact, low-noise, and wideband design suitable for Ka-band millimeter-wave applications.

The design of a 15–28 GHz broadband low-noise amplifier (LNA) is presented, employing a magnetically coupled resonator (MCR) to achieve simultaneous bandwidth extension and output matching. To address the increased in-band ripple that occurs when enhancing bandwidth with limited on-chip inductor values, an emitter-collector feedback transformer is introduced to mitigate the MCR ripple by generating an additional pole. This approach enables bandwidth expansion while maintaining minimal gain ripple. The LNA is implemented in 90-nm SiGe BiCMOS technology, occupying a core area of$0.11~\text {mm}^{2}$. It achieves a peak gain of 19.3 dB across a 3-dB bandwidth of 15–28 GHz, with a gain ripple of 0.75 dB within the 16–26.7 GHz range. The measured noise figure (NF) ranges from 2.9 to 3.9 dB. Additionally, the input 1-dB gain compression point ($\text {IP}_{\text {1 dB}}$) remains stable between −27 and −24.5 dBm throughout the entire 3-dB gain bandwidth. The LNA consumes 9.7 mW of power from a 1.2 V supply.

Neural network (NN) operation has high requirements for storage resources and parallel computing, which bring huge challenges to the deployment of NNs in Internet-of-Things (IoT) devices. Consequently, this work proposed a low-power NN architecture, comprising an energy-efficient NN processor and a Cortex-M3 host processor to achieve state-of-the-art (SOTA) end-to-end inference at the edge. The innovations of this article are as follows: 1) to minimize the bit width of the weight while keeping the loss of accuracy within a small range, cross-layer error tolerance has been analyzed, and mixed precision quantization has been adopted for cross-layer mapping; 2) dynamic reconfigurable tensor processing unit (DR-TPU) with approximate computing has been proposed, which brings$1.45\times $computing energy reduction within 0.46% accurate loss in ResNet-50; and 3) a customized input feature map (IFM) reuse and over-writeback strategy has been adopted, eliminating the recurrent fetching from the on-chip and off-chip memories. The times of on-chip storage access can be reduced by 25%–60%, and the capacity of on-chip memory can be reduced to half of the original. The processor has been implemented at 28-nm CMOS technology. Combining the above work, the proposed architecture can achieve a 53.1% reduction of power and 17.2-TOPS/W energy efficiency.

This paper proposes a dual-path CMOS RF-to-DC rectifier operating at 2.45-GHz with an ultra-wide high power conversion efficiency (high-PCE) input range. A new rectifier based on all NMOS rectification devices (all-NMOS) is proposed for high-power path and a modified cross-connected (CC) rectifier is designed for low-power path. The control signal for path switching is adaptively generated by auxiliary circuits without external reference or supply. The input power range with high-PCE is extended by the proposed architecture to meet the various application scenarios of energy harvesting. Implemented in a 0.18-μm standard CMOS technology, the proposed dual-path rectifier achieved a sensitivity of −20.7dBm, and it has two peak PCEs of 57% and 62% at −15dBm and 1.6 dBm, respectively. Furthermore, the PCE of the proposed dual-path rectifier can be maintained above 20% with a 27 dB input range from −22 to 5 dBm when operating at 2.45-GHz with a 50-k$\Omega$ load.

This paper presents an inductor-less RF transmitter (TX) based on harmonic-rejection edge combiner (HREC) and delay-locked loop (DLL) to suppress the $3^{\mathrm{rd}}/5^{\mathrm{th}}$ harmonics for low-power biomedical applications. The proposed HREC utilizing a resistance-divider technique not only achieves $9\times$ frequency multiplication but also simultaneously cancels the $3^{\mathrm{rd}}/5^{\mathrm{th}}$ harmonics by shaping the output voltage waveform. To reduce the power consumption, the multi-phase input signals for the HREC are generated by a DLL at a relative low frequency. The TX is designed in a 65-nm CMOS process with a core area of 0.05 mm2. The simulation results show that the proposed TX achieves the 3rdand 5thharmonics rejection > 40 dBc and > 52 dBc, respectively. It delivers a −16 dBm output power to a 50 $\Omega$ load without using any on- and off-chip inductors. The TX consumes a total DC power of 1.1 mW from a supply voltage of 1 V.

In this paper, the dual common-mode (CM) resonance technique is proposed for lowering the phase noise (PN) and flicker PN corner of LC voltage-controlled oscillators (VCOs) across wide tuning range. The dual CM resonator can provide high and resistive input impedance across a wide$2^{\mathbf {nd}}$harmonic band without dedicated tuning. It can both prevent the tank-loading effect and reshape the output waveform. Novel implementation methods are demonstrated to realize dual CM resonance at high frequencies. For comparison, both the dual CM resonance VCO and a reference one with a tail filter are fabricated in 65-nm CMOS, achieving the measured frequency range of 8-11.15 and 7.98-11.3 GHz, respectively. In 1/f2region, the proposed VCO shows an average PN of −139 dBc/Hz and the FOM of 190-192.3 dBc/Hz across the band, leading to an excellent FOM$_{\mathbf {T}}$of larger than 200.3 dBc/Hz. The reference VCO shows the average PN and FOM of -137.7 and 190.5 dBc/Hz. In 1/f3region, the former exhibits a low flicker PN corner of 280–350 kHz while the latter’s flicker PN corner varies largely from 290 to 950 kHz across the band. Both VCOs’ cores consume about 5 mW at 1 V supply and occupy approximately 0.13 mm2.

This paper presents two high-efficiency charge pumps (CPs) by utilizing the gate voltage boosting technique (GVBT). Unlike traditional bulk-CMOS and all-NMOS CPs, an input bias voltage is independently applied to the gate terminal, and it improves the current driving capability without the need of large pumping capacitors or high-frequency clocks. Meanwhile, the GVBT decouples the state of transistors from the clocks connected to the pumping capacitor, and it can eliminate the reversion loss in both main and auxiliary circuits. Fabricated in a 0.18-$\mu \text{m}$standard CMOS technology, the single-stage all-NMOS CP achieved a maximum output voltage of 6.589 V and a peak power efficiency of 80.08%. We also implemented the bulk-CMOS CP with GBVT for comparison, the single-stage all-NMOS CP achieved$\sim 1.24\times $more output voltage than the bulk-CMOS CP under a load current of 1.5 mA. The voltage errors of the all-NMOS CP between the analytical and the measured results are less than 7%.