Analog-based neural network accelerators outperform digital-based accelerators in energy efficiency by trading accuracy. Analog computation is susceptible to hardware stochastic variability, incurring in limited signal-to-noise and aggravating for compact and low power applications. Here we introduce A-Connect, anex situstatistical methodology to improve analog neural network resilience against stochastic variability. Our methodology achieves state-of-art performance in analog environments with heavy stochasticity levels by injecting noise during the neural network forward propagation and considering the same injected noise during the backward propagation. Furthermore, we developed a Keras/Tensorflow library with fully-connected and convolutional layers versions using our training methodology, which can be coupled easily to standard machine learning platforms. We present simulation results applying the A-Connect methodology to popular DNN models, like LeNet-5 for MNIST dataset, AlexNet, VGG-16, and ResNet-20 for the CIFAR-10 dataset, and ResNet-18 for CIFAR-100 dataset. When validating the CIFAR-10 or CIFAR-100 recognition tasks, the results with the A-Connect methodology showed an improvement over the baseline model of around 15 to 68 percentage points for the median accuracy at a 70% of stochastic variability. The deviation of the results with A-Connect is around 20X lower than the baseline at this level of stochasticity. A-Connect also showed the best performance when compared to otherex situapproaches, while having comparable results toin situ, and hybrid (i.e., usingex situandin situapproaches) methods in the literature. We anticipate that the A-Connect methodology could enable emergent memory technologies, such as ReRAM and PCM, for accurate computation-in-memory applications.

The proliferation of multiple communication standards and the constant data-rate enhancement set feed-forward ring oscillators (FFRO) as prominent clock generation circuits due to their wide operating frequency range. However, signal-to-noise ratio (SNR) and phase noise masks appear as major concerns when clock sources intend large tuning ranges. In this work, we developed a phase noise model based on a multi-loop control system theory applied to FFROs. Besides showing a good match between the proposed model and Spice simulations, the model give qualitative insights to adjust the extended frequency range with awareness of the phase noise performance. For instance, we show that it is possible to achieve a 6dB phase noise performance improvement for a given feed-forward strength.

Multi-protocol support applications and complex systems-on-chip demand several clock sources to fulfill the diverse data exchanging. This paper presents an fmax/ fmin=3D 15000 tuning range feed-forward differential ring oscillator to reduce the total number of required clock references with no additional frequency dividers. Secondary feed-forward loops allow the oscillator to increase 3X the maximum oscillation frequency up to 1.5GHz while achieving a 100kHz minimum frequency. The proposed feed-forward oscillator generates a kHz-to-GHz output frequency occupying an area of 0.05mm2in a pure digital 180nm CMOS process node. Post-layout simulations report an RMS jitter of [email protected] with a maximum [email protected] power consumption and a phase error of 1.4°@1.5GHz.

Modern and miniaturized ASICs enable the development of anatomically constrained applications within the biomedical framework, such as smart contact lenses. Recent works report lenses receiving power and communicating through inductive coupled links. However, the efficiency of an inductive link depends highly on alignment and distance between coils, thus encouraging the exploration of other techniques to power and communicate a smart contact lens. Intra-body links emerge as an alternative to inductive ones for wearable devices, with promising path-loss results reported in previous works. Here, we evaluate the feasibility of powering a smart contact lens through an intra-body link. We propose a simplified 3D-FEM human-head model to estimate channel losses in a real contact lens situation. Then, we validate the pathloss estimations on the head through a human arm experiment, and comparison against a simplified 3D-FEM human-arm model. Based on our analysis, we estimate retrieved power of μW level, demonstrating the feasibility of using an intra-body link to power a smart contact lens.

High-speed serial link design has become an industry spotlight due to the wide use of data-driven applications. To avoid possible over-estimated transceivers designs, the IEEE 802.3bj standard introduced the channel operating margin (COM) as a system-level metric approach. Instead of evaluating traditional individual metrics, COM validates a serial link performance based on the global system operation. Although COM metric advantages are already highlighted in the literature, reported works only utilize this metric to characterize existing channels. This work explores the COM metric as a potential transceiver design methodology, reviewing COM performance with different equalizer architectures.

Current solutions for low-cost and secure systems have ended up trading effective encryption schemes for lighter encryption schemes to ensure longevity in battery-powered applications. Here we demonstrate the potential to apply an effective and lighter encryption scheme, such as AES-256, in a low-cost battery-powered systems-on-chip (SoC) without demanding excessive energy. We accelerated AES-256 with a custom instruction along with an enhanced memory access scheme. Measurement results from a fabricated SoC featuring a RISC-V based 32-bit processor indicate a 900 fold improvement of AES-256 computing energy efficiency compared to pure-software implementations. The memory access improves the energy by 3 times an standard push-pull hardware implementation.

Automatic standard cell layout generation employs algorithms for transistor folding, placing, and routing. Reported standard transistor placement algorithms neglect to consider, in advance, the full netlist and the routing to generate clean layouts. Here, we introduce a placement algorithm with an optimization for complete routing and pre-layout algorithm awareness. The algorithm applies pseudo-boolean satisfiability to determine the minimum-width transistors in the cell. Placement optimization provides route-awareness to circumvent routing congestion according to pins location. The proposed algorithm is implemented in a full automatic standard cell generation procedure, fulfilling a commercial 180nm technology node design rules. Final generated layouts are 30% more routable than the base SAT formulations, enabling 100% routing in complex cells.

Agile hardware design strategies have shown a fast adoption in academia and industry by bringing ideas from the software development side. However, adopted design methodologies exhibit traditional verification scenarios based on handmade testbenches. Here we describe a verification methodology for RISC-V-based processors with human-independent testbenches creation, employing high-effort verification methods throughout all processor design cycle. We demonstrated the methodology by performing verification tests in a single-issue in-order (SIIO) 32-bit RISC-V ISA based processor described in Chisel. In contrast to standard verification methods, the proposed methodology can detect bugs hard to isolate even after final FPGA implementations in-field. The generated test programs show higher coverage metrics, and χ 30 fewer instructions compared to official RISC-V torture unit tests.

Physical unclonable functions (PUFs) should exhibit unique and highly reliable key values. However, commonly reported PUF architectures involve entropy sources sensitive to small environmental perturbations that produce unsteady final key responses. Here we report a stable PUF bitcell that overcomes sensitivity challenges by using the capacity to fuse back the random generated key values into the PUF itself constituted as a non-volatile random access memory (NVR). The proposed PUF bitcell is based on floating gates (FG) NVR cells implemented in a standard CMOS technology without additional masks or fabrication steps. Measurement results from a fabricated PUF macro in a 0.18μm CMOS node indicate an average less than 3% unstable bits for bitcells without post-processing. PUF key bits of programmed cells are 100% stable after applying the UP/DOWN-count stabilization scheme.

Modern system-on-chip (SoC) applications commonly comprise multiple voltage domains to save power consumption according to the required circuit performance. Level shifter (LS) blocks usually interface these power domains to guarantee fitting voltage levels for the control signals among low supply and high supply voltage domains. Using only thin-oxide transistors for LS implementations enables their subsequent integration into the digital domain of an SoC and enhances circuit speed performance. Nevertheless, thin devices entail overvoltage issues when the voltage difference between the supply domains to be communicated is large, e.g. during the SoC's power-up sequence. Here we propose an LS architecture along with a three-devices protection scheme to avoid powering-up overvoltage issues, which have been neglected by reported LS works, validated through simulations. The results disclose a maximum operating frequency of 400MHz and an average energy-per-transition of 470fJ.

The instruction set architecture (ISA) specifies a contract between hardware and software; it covers all possible operations that have to be performed by a processor, regardless of the implemented architecture. Verifying the instruction execution against a golden execution model following the ISA is becoming a common practice to verify processors. Despite many potential applications, existing verification frameworks require an extensive test set to cover most of the processor states. In this paper, we suggest a verification scheme combining two different domains, simulation- and formal-verification, establishing a methodology for exclusive error detection. The first approach drives automatic program generation using genetic algorithms to maximize coverage of the test and the contrast against an instruction set simulator. The second is a formal verification approach, where an interface carries specific processor states according to the ISA specification. By combining these two, we present a reliable way to perform more accurate instruction verification by increasing processor state coverage and formal assertions to detect different kinds of errors. Compared to extensive torture test sets, this approach reaches a more significant number of internal states by taking advantage of the exercised abstractions. Among remarkable results to highlight, the proposed approach detected a RISC-V ISA specification gap revealing ambiguity from two different verification perspectives.

This paper explores the impact of the equivalent series resistor (ESR) on the stability of linear regulators. While traditional compensation schemes seek to mitigate the effect of ESR on regulator performance, this paper shows the advantages of using ESR as a lag-lead compensator to improve phase and gain margin without regarding possible low ESR values. The work also presents an adaptive biasing strategy: 1) to reduce the variation of nondominant poles; 2) to improve efficiency for low load-currents.

Loop gain adaptation techniques that explore the dynamics of digital phase-locked loops, and clock and data recovery circuits through the autocorrelation function are becoming popular. This work proposes an adaptation technique based on the cross-correlation function between bang-bang phase detector and loop filter outputs instead. Filtering properties of the cross-power spectral density enhance the observability of loop dynamics allowing adaptation while maintaining the phase margin at a safe value. Compared to previously reported methods, the proposed adaptation technique directly tracks the CDR dynamics distinctively enhancing the gain adaptation algorithm.

This paper introduces a family of three resistor-less low-power, low-area and trim-free current references with low PVT sensitivity. The proposed current sources achieve tens of nano-Ampere current consumption with a temperature coefficient down to 182ppm/°C. The proposed family of current sources are enabled to operate within the 3.3V I/O voltage domain, to avoid additional power consumption from internal regulation, and they are implemented in a 180nm standard logic CMOS process.

This paper presents a low-cost technique to reduce offset voltage of a dynamic comparator. The proposed method is based on output-data phase measuring through a digital implementation without impacting offset accuracy. The technique requires less than 500ns to achieve convergence and calibration without needing to break the signal path associated to the comparator during regular link operation. An on-a-chip emulated channel and front-end with a sampling circuit has been implemented in 130nm CMOS along with a chip-scope capability to measure eye diagrams at the input of the sampler. Although the concept has been implemented in a low speed interface considering available technology, the implementation shows potential to port the proposed offset correction scheme to a state-of-the art process node applied to links featuring data rates with tens of Gb/s.

This work presents a fully integrated three-stage low-dropout regulator (LDO) for system-on-chip applications. The circuit is compensated with the reverse nested miller technique using current buffers (RNMCCB). Based on the results of a complementary Pole-Zero analysis, and the biasing of the power transistor in the triode region, it was possible to size the LDO such that the lowest reported area is achieved for loads up to 50mA. A dynamic biasing circuit is used to speed up the transient response and minimize the settling time. The regulator has been implemented in a TSMC 130nm CMOS technology and occupies an active chip area of 0.007 mm2including the capacitors.

An energy-efficient 4:1 multiplexer (MUX) operating at 40Gb/s using ETSPC logic is presented. For the first time, a single-phase clock digital-logic-based MUX operating with data rates above 20Gb/s is demonstrated. A new multifunctional 2:1 MUX cell with reduced number of transistors is proposed, and an efficiency of 21.5μW/Gb/s at 40Gb/s, gives the best power-efficiency reported. The MUX is designed in a 45nm SOI CMOS technology with 1V supply.

For more than seventy years, all the development in digital electronics have been founded on Shannon's work based on the fact that Boolean logic operators, OR, AND and NOT, can form a computationally complete logic framework. We propose a new paradigm in logic circuit design using material implication logic operators, different from the traditional logic gates in implementation and operation. In this paper we present early evidences, with experimental silicon results, showing that this new logic framework significantly improves performance, power and speed, over an equivalent conventional-logic framework in CMOS. This new computing paradigm would enable the continuance of increasing computing functionality and performance with decreasing cost in silicon technologies.

We present a compact dual-modulus prescaler working at 50GHz without using inductors. A novel divider-by-2/3 in a reduced logic with minimum number of transistors is presented. For the first time, a single-phase clock digital-logic-based prescaler operating at frequencies in the mm-wave band is demonstrated. A power consumption of 130.2µW at 50GHz, gives the best power-efficiency reported. The prescaler is designed in a 45nm SOI CMOS technology with 1V supply.