Accurate detection and fast resolution of device measurement is one of the most intriguing test challenges now and in the foreseeable future. This is especially true for those devices with input/output (IO) speeds and electrical characteristics which exceed the automatic test equipment (ATE) edge placement accuracy (EPA) and/or overall tester accuracy (OTA). The tester derating factor (TDF) methodology described in this paper is an evolving solutions matrix being used by the Intel Chipset Engineering Group to turn this challenge into a competitive advantage. This paper describes how the TDF matrix can help engineers take full advantage of existing equipment, including testing devices beyond the vendor specified/published EPA/OTA, and suggests ways for the ATE vendors to partner with users to enable this capability on existing/future testers.

An application of the D-algorithm in generating tests for MOS circuit faults is described. The MOS circuits considered are combinational and acyclic but may contain transmission gates and buses. Tests are generated for both the stuck type faults and the transistor faults (open and short). A logic model is derived for the MOS circuits. In addition to the conventional logic gates, a new type of modeling block is used to represent the "memory" state caused by the "open" transistors. Every fault, whether a stuck type fault or a transistor fault, is represented in the model as a stuck fault at a certain gate input. For generating tests, however, the D-algorithm needs modification. The singular cover and the D-cubes for the new gate include some memory states. To handle the memory state, an initialization procedure has been added to the consistency part of the D-algorithm. The procedure of modeling and test generation is finally extended to transmission gates and buses.