VLSI engineers have traditionally used a variety of CAD analysis tools (e.g. SPICE) to deal with variability.As we go into deep sub micron issues, the analysis is becoming harder due to many secondary effects becoming primary. Panelists will debate the variability trend and present the order of importance of many variability trends (Vdd, Vt, Interconnect, Leff, Gate Width) and their impact on design tools and methodologies.What new design tools, new modeling methodologies, and new (or old) design styles will combine to address variability?Will conservative design to accommodate variability halt the progress of Moore's Law?Is life as we know it over, or are we facing an opportunity for innovation in tools and design that will move us forward over the barriers that technology has placed in our path?.

Although many physical limitations have been reached in modern micro-lithography, printed critical dimensions continue to shrink according to the International Technology Roadmap for Semiconductors (ITRS) [1]. To meet the demands imposed by this guideline, the traditional separation between design and manufacturing communities is being bridged. Many EDA tools package manufacturing data for delivery into established simulation engines for design verification. However, none of them provide practical implementations of design optimizations at an early stage in the design flow.This paper presents an automated layout modification flow for metal layers with the goal of enhancing manufacturability. It can easily be deployed in a current custom design flow in a way that is visible to designers. The result of this scheme is improvements to process windows and yield, while minimizing circuit performance detractors. The flow is verified through analyses of both the impact on circuit performance and the benefit to manufacturability. It has been implemented in a state-of-the-art 65 nm chip design. Both silicon yield and electrical performance data are currently being collected and analyzed.