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Athanasios E. Papathanasiou

dblp:55/3030 · DBLP profile ↗
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6ranked-venue papers
3as first author
0since 2021 · last 2010
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 2 first-authorComputer networks · 1Software engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
4 papers
Memory systems · 36% Hardware reliability and fault tolerance · 32% Storage systems · 11%
Computer networks
1 paper
Internet architecture and protocols · 100%

Topics — the 10 heaviest of 12, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
cache
0.122010
Explaining cache SER anomaly using DUE AVF measurement · HPCA 2010
Energy Efficient Prefetching and Caching (Awarded Best Paper!) · USENIX ATC, General Track 2004
Hardware reliability and fault tolerance › soft errors
architectural vulnerability factor
0.112010
Explaining cache SER anomaly using DUE AVF measurement · HPCA 2010
Hardware reliability and fault tolerance
soft errors
0.112010
Explaining cache SER anomaly using DUE AVF measurement · HPCA 2010
Storage systems › i/o scheduling
disk scheduling
0.112007
Competitive prefetching for concurrent sequential I/O · EuroSys 2007
Memory systems › cache
prefetching
0.112007
Competitive prefetching for concurrent sequential I/O · EuroSys 2007
Energy-efficient computing
power management
0.012004
Energy Efficient Prefetching and Caching (Awarded Best Paper!) · USENIX ATC, General Track 2004
Memory systems › cache management
prefetching and caching
0.012004
Energy Efficient Prefetching and Caching (Awarded Best Paper!) · USENIX ATC, General Track 2004
Internet architecture and protocols › middlebox
network address translation
0.012002
KNITS: Switch-based Connection Hand-off · INFOCOM 2002
High-performance computing › cluster computing
server cluster
0.012002
KNITS: Switch-based Connection Hand-off · INFOCOM 2002
Performance modeling and evaluation
workload characterization
0.012007
Competitive prefetching for concurrent sequential I/O · EuroSys 2007

Methods — techniques the papers use, named apart from their topics

simulation · 0.1proton beam irradiation · 0.1offline optimal policy analysis · 0.1network address translation · 0.1connection splicing · 0.1competitive analysis · 0.1
YearPublicationVenuePosition
2010 Explaining cache SER anomaly using DUE AVF measurement
abstract
We have discovered that processors can experience a super-linear increase in detected unrecoverable errors (DUE) when the write-back L2 cache is doubled in size. This paper explains how an increase in the cache tag's Architectural Vulnerability Factor or AVF caused such a super-linear increase in the DUE rate. AVF expresses the fraction of faults that become user-visible errors. Our hypothesis is that this increase in AVF is caused by a super-linear increase in ¿dirty¿ data residence times in the L2 cache. Using proton beam irradiation, we measured the DUE rates from the write-back cache tags and analyzed the data to show that our hypothesis holds. We utilized a combination of simulation and measurements to help develop and prove this hypothesis. Our investigation reveals two methods by which dirty line residency causes super-linear increases in the L2 cache tag's AVF. One is a reduction in the miss rates as we move to the larger cache part, resulting in fewer evictions of data required for architecturally correct execution. The second is the occurrence of strided cache access patterns, which cause a significant increase in the ¿dirty¿ residency times of cache lines without increasing the cache miss rate.
Arijit Biswas, Charles Recchia, Shubhendu S. Mukherjee, Vinod Ambrose, Leo Chan, Aamer Jaleel, Athanasios E. Papathanasiou, Mike Plaster, Norbert Seifert
HPCA7
2007 Competitive prefetching for concurrent sequential I/O
abstract
During concurrent I/O workloads, sequential access to one I/O stream can be interrupted by accesses to other streams in the system. Frequent switching between multiple sequential I/O streams may severely affect I/O efficiency due to long disk seek and rotational delays of disk-based storage devices. Aggressive prefetching can improve the granularity of sequential data access in such cases, but it comes with a higher risk of retrieving unneeded data. This paper proposes a competitive prefetching strategy that controls the prefetching depth so that the overhead of disk I/O switch and unnecessary prefetching are balanced. The proposed strategy does not require a-priori information on the data access pattern, and achieves at least half the performance (in terms of I/O throughput) of the optimal offline policy. We also provide analysis on the optimality of our competitiveness result and extend the competitiveness result to capture prefetching in the case of random-access workloads.
Chuanpeng Li, Athanasios E. Papathanasiou
EuroSys3
2005 Aggressive Prefetching: An Idea Whose Time Has Come
Athanasios E. Papathanasiou, Michael L. Scott
HotOS1
2004 Energy Efficient Prefetching and Caching (Awarded Best Paper!)
Athanasios E. Papathanasiou, Michael L. Scott
USENIX ATC, General Track1
2002 KNITS: Switch-based Connection Hand-off
abstract
This paper describes a mechanism allowing nodes to hand-off active connections by utilizing connection splicing at an edge-switch serving as a gateway to a server cluster. The mechanism is primarily intended to be used as part of a content aware request distribution strategy. Our approach uses an extended form of network address translation which maps inbound connection information (ie., address, port, and sequence number) to a separate outbound connection. A key difference in our approach is that while the switch performs network address translation and TCP splicing, the actual hand-off is triggered by the back-end nodes. This relieves the switch of performing any application layer responsibilities. Nodes may hand-off connections by first initiating a new connection to the destination and then sending a message to the gateway which splices the two connections together. The gateway modifies subsequent packet headers in order to create a transparent hand-off. This mechanism requires no modification to the operating system on the servers or the clients and supports HTTP/1.1 persistent connections and pipelined requests. To test our design, we implemented a soft-switch using Linux Netfilter which includes the extended network address translation. We provide some preliminary performance analysis and make recommendations for future work.
Eric Van Hensbergen, Athanasios E. Papathanasiou
INFOCOM2
1998 Lightweight Transactions on Networks of Workstations
abstract
Although transactions have been a valuable abstraction of atomicity, persistency, and recoverability, they have not been widely used in programming environments today, mostly because of their high overheads that have been driven by the low performance of magnetic disks. A major challenge in transaction-based systems is to remove the magnetic disk from the critical path of transaction management. We present PERSEAS, a transaction library for main memory databases that decouples the performance of transactions from the magnetic disk speed. Our system is based on a layer of reliable main memory that provides fast and recoverable storage of data. We have implemented our system as a user-level library on top of the Windows NT operating system in a network of workstations connected with the SCI interconnection network. Our experimental results suggest that PERSEAS achieves performance that is orders of magnitude better than traditional recoverable main memory systems.
Athanasios E. Papathanasiou, Evangelos P. Markatos
ICDCS1