We propose a UNet-based foundation model and its self-supervised learning method to address two key challenges: 1)lack of qualified annotated analog layout data, and 2)excessive variety in analog layout design tasks. For self-supervised learning, we propose random patch sampling and random masking techniques automatically to obtain enough training data from a small unannotated layout dataset. The obtained data are greatly augmented, less biased, equally sized, and contain enough information for excessive varieties of qualified layout patterns. By pre-training with the obtained data, the proposed foundation model can learn implicit general knowledge on layout patterns so that it can be fine-tuned for various downstream layout tasks with small task-specific datasets. Fine-tuning provides an efficient and consolidated methodology for diverse downstream tasks, reducing the enormous human effort to develop a model per task separately. In experiments, the foundation model was pre-trained using 324,000 samples obtained from 6 silicon-proved manually designed analog circuits, then it was fine-tuned for the five example downstream tasks: generating contacts, vias, dummy fingers, N-wells, and metal routings. The fine-tuned models successfully performed these tasks for more than one thousand unseen layout inputs, generating DRC/LVS-clean layouts for 96.6% of samples. Compared with training the model from scratch for the metal routing task, fine-tuning required only 1/8 of the data to achieve the same dice score of 0.95. With the same data, fine-tuning achieved a 90% lower validation loss and a 40% higher benchmark score than training from scratch.

Determining a channel’s characteristics is a fundamental step for designing a high-speed link system. By identifying the properties of the channel, designers can gain insights into how to transmit a signal with low distortion and optimize a transceiver’s architecture. As the channel’s characteristics can be identified by analyzing its single-bit pulse response (PR), obtaining an accurate PR plot is critical for reliable channel characterization. Therefore, it is preferred to measure the PR in situ to minimize the parasitic effects. In this work, we introduce a novel approach for measuring PR in situ, designed to quickly and accurately generate undistorted plot results. To prove the efficacy of the proposed method, we designed an on-chip sampling scope circuit and fabricated a test chip in 28-nm CMOS technology. While being able to measure a distortion-free PR, the proposed method demonstrates a more than$10^{5}$times faster pulse acquisition rate than prior arts.

We propose a fast algorithm to optimize on-chip equalizing link design utilizing a particle swarm optimization (PSO) method. Finding the optimal design parameters of an equalizing link requires too much computation time, because the dependency between design parameters and performances is too complex, while design space is too large. The proposed algorithm greatly reduces the optimization time by utilizing the superior efficiency of PSO in heuristic search. In experiment, on average, the proposed algorithm optimized a link design$168\times $faster than the previous state-of-the-art result, requiring only 1/256 evaluation counts, and reduced computation time from about 2 h to 45 s.

This paper presents compact single-ended wireline transceivers with software-generated receiver front-ends. The developed software framework significantly shortens the physical design time of 1/N-rate wireline receiver front-ends. The physical layouts of various receiver front-ends were software-generated in four different CMOS technology nodes (28 nm, 40 nm, 65 nm, and 90 nm) with four different front-end architectures targeting various data rates. In the post-layout simulation, the receiver front-ends generated within a second by the software achieved nearly the same performances as the manually-designed receiver front-ends that require more than about 30 hours of design time. For demonstration, we generated 8 Gb/s full-rate, 10 Gb/s half-rate, 12 Gb/s, and 20 Gb/s quarter-rate receiver front-ends, and fabricated them with a manually-designed feed-forward equalization transmitter in 28 nm CMOS process. The transceivers were measured with the data rate up to 20 Gb/s while consuming 1.39 pJ/b at the channel loss of −9.2 dB. The transceiver with software-generated receiver achieved the highest data rate per area as well as the smallest area among the relevant prior arts while reducing the physical design time of the receiver front-end by more than 140,000 times.

We propose a speculative divide-and-conquer (SDnC) method that enables optimization of a large analog/mixed-signal (AMS) circuit. Because modules of AMS circuits strongly interact with neighbor modules, they cannot be optimized individually. Therefore, design parameters of all modules must be co-optimized for the global optimization, and thus, the design space exponentially grows with the circuit size. Although metaheuristic algorithms can enhance optimization efficiency, they cannot handle very large circuits due to the exponentially increased size of design space to explore. The proposed method utilized the divide-and-conquer (DnC) strategy in the circuit optimization while taking into account modules’ interactions, allowing modules to be individually evaluated and optimized. Therefore, this DnC-based optimization method hierarchically and systematically reduces both the optimization complexity and the evaluation complexity, and thus, this method is very scalable with the circuit size. The proposed method can also be combined with other metaheuristic algorithms such as particle swarm optimization (PSO) or artificial intelligence for faster optimization. In experiment, the proposed method enabled optimization of a high-speed link transmitter that has 2400–15 000 transistors and 45–47 independent design parameters for the first time. The optimization time was improved by 43 and three orders of magnitudes compared to parameter sweep and PSO, respectively. The penalties of speed-up by DnC were only 3.4% and 9.3% estimation errors in power consumption and eye height, respectively. Because of the greatly improved speed, the proposed method also enables quantitative analysis on performance-power tradeoff of a large AMS circuit.

This paper presents a compact single-ended inverter-based transceiver with swing improvement for short-reach links. The low output impedance of the transmitter enlarges the output swing and the eye size to overcome large single-ended noise while relaxed impedance matching provides good signal integrity. For good area efficiency, the proposed transmitter utilizes an inverter driver which is much smaller than the conventional source-series termination driver and thus occupies only$42.5 ~\mu \text{m}^{2}$. By taking the advantage of a large signal swing, the receiver consists of only four slicers and latches to minimize area overhead and to simplify the design. The transceiver was fabricated in 28-nm CMOS technology and tested at supply voltage of 1.13 V. The transmitter achieved a large output swing of 850 mV, which is 50.4 % larger than the conventional source-series termination transmitter. At the far-end of a channel consisting of a 1 m SMA cable and a 17 mm printed circuit board trace, the transmitter achieved eye openings of 440 mV and 234 mV at 16 Gb/s (−2.7 dB) and 20 Gb/s (−8 dB), respectively. Even with a large switching noise of 100 mV, thein-situeye at the receiver was measured 114 mV with 7.4 dB loss.

We present the first FFE SST TX layout generator enhanced by various software techniques including a GUI-based template engine. Seven different DRC/LVS-clean TXs were generated in multiple technologies (40nm/65nm/90nm CMOS) for the first time, and achieved adequate maximum data rates: 36Gb/s with 40nm in post-layout simulation; 14Gb/s with 65nm in measurement. Total generation time was less than 5 days, including iterative parameter tuning by a human designer and computation (30 minutes for TX core, 8 hours for power network). Fast post-layout analysis of TX’s performance-power trade-off was enabled by the presented generator for the first time.

For the first time, we prove that 7.8-Gb/s single-ended signaling through a highly reflective channel is feasible at low energy cost by an energy-efficient many-tap decision feedback equalization (DFE) receiver (RX). The reported data rate of 7.8 Gb/s is the fastest data rate that has been achieved through a single-ended highly reflective channel that has more than five taps of postcursor reflective intersymbol interference. Compared with the prior arts, the target multidrop has the most in-band notches: ten notches. To compensate for large reflection by many notches, the RX exploits the DFE with the largest tap count of 20 that has been never used in single-ended signaling before. Low-power circuit techniques such as a current-integrating summer and double-tail sense amplifiers were adequately adopted and engineered to reduce large power dissipation by many taps. The RX was fabricated in a 65-nm CMOS technology and occupies only 0.014 mm2. The energy efficiency was measured to be only 2.9 pJ/b at 7.8 Gb/s with 0.9-V supply, proving that fast single-ended signaling through a highly reflective channel is feasible at low energy cost by many-tap DFE if low-power circuit techniques are adequately applied. The horizontal and vertical eye sizes were measured to be 0.12 UI and 34 mV, respectively, at a bit error rate of-12.

In this paper, we propose a code inversion encoding technique to improve the read margin of a cross-point phase change memory (PCM). The proposed technique reduces the maximum number of low resistance state cells which significantly reduce read margin by increasing sneak current. Therefore, the proposed scheme can significantly improve the read margin of the cross-point PCM. To verify the improvement of read margin by the proposed technique, we simulated and compared read margins of various arrays with and without the proposed technique. According to the simulation, our technique improves the read margin by 102% or equivalently allows to increase the array size by 91.6% without decreasing for the read margin. The results show that the proposed technique greatly improves the read margin.

This paper presents a sub-10 nW bandgap reference (BGR) circuit that implements both voltage and current references in one circuit. The BGR circuit was implemented with a 0.18μm CMOS process and generates voltage and current references of 1.238 V and 6.64 nA while consuming 9.3 nW. The voltage and current references show standard deviations of 0.43 % and 1.19 % with temperature coefficients of 26 ppm/°C and 283 ppm/°C, respectively.

This paper presents a body-channel communication (BCC) transceiver adopted with decision feedback equalization (DFE). The proposed transceiver, fabricated in 65-nm CMOS process, achieves reliable (BER-6) data rates of 150 Mb/s (16.6 pJ/b), and 100 Mb/s (23.5 pJ/b) over 20-cm and 1.3-m channels on human limbs. The transceiver occupies a total core area of 5580 qm2, which is less than 1% compared to any previously-presented work.

This paper presents an amplifier-less and digital-intensive current-to-digital converter for biosensors. The proposed circuit achieves a first-order noise shaping of the quantization error without any continuous-time feedback circuit. Also, it minimizes static power consumption by employing a single-ended current-steering digital-to-analog converter (DAC) which flows only the same current as the input. The effect of dynamic switching noise become input-independent constant by adopting switching averaging algorithm. The implemented circuit in 0.35pm CMOS converts an input range of 2.8pA to 15b digital output in about 4ms, while consuming 16.8pW.

In this paper, we propose a search algorithm to find the worst operation scenario of a cross-point array of a phase-change random access memory to enable a precise read margin evaluation. The search algorithm utilizes a particle swarm optimization method to find the worst scenario quickly and efficiently. In an experiment, the proposed algorithm improves the search speed by 39.3× compared with the previous algorithm. With the improved search speed, the proposed algorithm could find the worst operation scenarios of large arrays whose worst operation scenarios had been only guessed before. In the experiment with a large array, the proposed algorithm proved that the worst high-resistance state read current can be 36× larger than the previous best guess. In the reliability test, the evaluation error of the worst read current found by the proposed algorithm is less than 0.2% with 99% probability. These results show that the proposed search algorithm can improve the precision and efficiency of the read margin evaluation in designing a cross-point phase-change memory array.

This paper presents an automatic resistive random access memory (ReRAM) SPICE model generator, which enables fast ReRAM circuit evaluation with standard SPICE. Our model generator automatically produces SPICE models of ReRAM devices and selectors from the measured I-V data to reduce too much time consumption in manual model development for ReRAM devices and simulation of the target ReRAM circuits. To verify our method, SPICE models for diverse ReRAMs were automatically generated from measured data and simulated with various circuits. The results show that our model can accurately describe the original data and allows fast quantitative evaluation of ReRAM circuits. Because developing SPICE models of ReRAMs and simulating them with circuits have been the critical time-consuming procedure in ReRAM research, these results show that our method enables early ReRAM evaluation.

An all-synthesizable current-mode transmitter driver for a USB2.0 high-speed (480 Mb/s) interface was proposed to enhance the design portability. The proposed driver was implemented using tristate inverter cells. It uses the differential current-mode architecture, with variable output voltage swing, and includes a predriver. It was also successfully applied to the 480-Mb/s USB2.0 TX driver with the synthesized serializer and phase-locked loop.

This paper disproves the worst read scenario of a ReRAM crossbar array. If the previously believed worst read scenario is not the worst one, the read margin evaluated based on the scenario can be incorrect. We explored for read scenario worse than the previously believed worst scenario by wisely sampling scenarios and iteratively searching for the worse one. In experiment, our algorithm successfully found the scenario worse than the previously believed one, disproving the previously believed worst read scenario. Our results show that the sensing window estimated by the incorrect previously believed worst scenario is 14 times as large as the estimation by the worst scenario found by our algorithm.

This paper proposes a technique to reduce the sample number of channel's pulse response required to optimize equalization coefficients. In our method, channel's pulse response is aliased in calculating equalization coefficients reducing the number of samples of the channel's frequency response. As a result, the computation time to acquire the channel's frequency response is greatly reduced. To demonstrate our method, equalization coefficients are calculated using the conventional and our methods and then compared. Since the necessary number of samples is reduced by 8 times at most in our method, the computation time is reduced up to by 7.01 times. For accuracy verification, we also calculated the equalized eye sizes using both methods. The calculated eye sizes are almost identical. These results show that using our method, engineers can accurately optimize equalizing transceiver design with reduced efforts to simulate channel's frequency response.

The time-periodic property of the LCD VCOM noise is utilized to reduce the effect of the VCOM noise on the mutual-capacitance measuring touch sensor placed on a LCD panel. The amplitude of the touch sensor driving signal (VSTM) can be reduced reliably down to 0.4 V with the reporting rate of 189 Hz, by using the following two methods. (1) The frequency of VSTM is set to (n+0.5)·fN, by synchronizing VSTM to a LCD gate driver signal with a referenceless CDR. fN is the inverse of the LCD VCOM noise period (TN) and n is a positive integer. (2) The reset period of the RX integrator is set to 2·TN.

This paper presents a modeling framework for fast design space exploration and optimization of equalized on-chip interconnects. The exploration is enabled by cross-layer modeling that connects the transistor and wire parameters to link performance, equalization coefficients, and architecture- friendly metrics (delay, energy-per-bit, and throughput density). Appropriate models are derived to speed-up the search by more than two orders of magnitude and make a million point design space searchable in less than two hours on a standard machine. With this approach we are able to find the best link design for target throughput, power and area constraints, thus enabling the architectural optimization of energy-efficient on-chip networks. For the same latency and throughput density, equalized interconnects optimized using the new methodology have up to 10x better energy-efficiency than optimized repeater interconnects.

This paper introduces a positive-feedback self-biasing technique for operational amplifiers (op-amps) which enables their power consumption to adapt to their environment: The power consumption of one of our op-amps scales almost linearly with load capacitance, input signal frequency, and output signal swing. Our op-amp is primarily intended for low power switched-capacitor applications. A voltage follower built in the MOSIS/AMI 0.5/spl mu/m process with our op-amp has a measured power consumption that varies between 1.38/spl mu/W and 90/spl mu/W, as the load capacitance varies from 1pF to 100pF.