This paper presents a novel path selection methodology to select paths for monitoring unexpected systematic timing effects. The methodology consists of three components: path filtering, path encoding, and path clustering. Given a large set of critical paths, in path filtering, the goal is to filter out paths that cannot be functionally sensitized. To explore the space of unexpected timing effects, a set of features are defined to encode paths into path vectors. Each feature is a source of concern that may potentially contribute to the cause of an unexpected timing effect. Finally, a kernel-based clustering algorithm is employed to group similar path vectors into clusters from which the best representative paths are selected for post-silicon monitoring. The effectiveness of our proposed methodology is demonstrated through experiments on an industrial ASIC design.

In optimizing high-performance designs, speed limiting paths (speed-paths) impact the performance and power trade-off. Timing tools attempt to model and capture all such paths on a chip. Due to the high performance nature of these designs, critical paths predicted by the timing tools often do not match the actual speedpaths found on silicon chips. Early silicon data therefore is used to identify the speedpaths, and further performance optimization is carried out by pushing the delays on these paths. In this context, the paper presents a novel data mining approach that analyzes a small number of identified speedpaths against a large number of non-speedpaths. The result of this analysis for each speedpath is a set of hypotheses explaining why the path is special. These hypotheses can be used in guiding the search for the root causes, or in predicting additional paths as potential speedpaths. We demonstrate the feasibility of this approach and summarize our findings based on analysis of silicon speedpaths collected from a 65nm microprocessor.

In test and diagnosis, one often runs into the situation that after analyzing a set of samples, a few of these samples are identified as being ¿special¿. Then, in a large population of samples one desires to identify all samples that are ¿similar¿ to the special samples. The process is called a similarity search. This paper presents a feature based similarity search approach and discusses three potential methods to implement this approach. These methods are (1) building a model to capture the characteristics of the non-special samples, (2) building a model to capture the characteristics of the special samples, and (3) searching for the hypotheses to explain individually why each sample is special. We apply similarity search to the speedpath analysis problem where special samples are special paths that limit the performance of silicon chips. The goal is to identify more paths in the design with similar characteristics to the speedpaths. The effectiveness of the three methods are analyzed based on speedpath data collected from a high-performance microprocessor.

Explaining the mismatch between predicted timing behavior from modeling and simulation, and the observed timing behavior measured on silicon chips can be very challenging. Given a list of potential sources, the mismatch can be the aggregate result caused by some of them both individually and collectively, resulting in a very large search space. Furthermore, observed data are always corrupted by some unknown statistical random noises. In this paper, we examine how trying to explain the mismatch observed on silicon can be classified as an ill-posed problem, where ill posed means that the solution may not be unique or stable. Thus, a small change in the observed response can have a large change in the predicted solution. To solve ill-posed problems, a statistical learning theory uses a principle called regularization. This paper proposes using a statistical learning method called support vector (SV) analysis to statistically analyze all known sources of uncertainty with the objective to rank which sources contribute the most to the observed mismatch. Experimental results are presented under different error assumption models to compare two kinds of SV ranking approaches to four other ranking approaches, where some use the idea of regularization and others do not. This paper is concluded by showing a self cross-validation approach to validate the ranking results when there is no true ranking available, as the case with actual silicon.

Explaining the mismatch between predicted timing behavior from modeling and simulation, and the observed timing behavior measured on silicon chips can be very challenging. Given a list of potential sources, the mismatch can be the aggregate result caused by some of them both individually and collectively, resulting in a very large search space. Furthermore, observed data are always corrupted by some unknown statistical random noises. To overcome both challenges, this paper proposes a statistical diagnosis framework that formulates the diagnosis problem as a regression learning problem. In this diagnosis framework, the objective is to rank a set of features corresponding to the list of potential sources of concern. The rank is based on measured silicon path delay data such that a feature inducing a larger unexpected timing deviation is ranked higher. Experimental results are presented to explain the learning method. Diagnosis effectiveness will be demonstrated through benchmark experiments and on an industrial design.

In high performance designs, speed-limiting logic paths (speedpaths) impact the power/performance trade-off that is becoming critical in our low power regimes. Timing tools attempt to model and predict the delay of all the paths on a chip, which may be in the millions. These delay predictions often have a significant error and when silicon is measured there is a large variation of path delays as compared to the prediction of the tools. This variation may be caused by process, environmental or other effects that are often unpredictable. It is therefore desirable to use early silicon data to better predict and model potential speedpaths for subsequent silicon steppings. In this paper, we present a novel machine learning-based approach that uses a small number of identified speedpaths to predict a larger set of potential speedpaths, thus significantly enhancing the traditional timing prediction flows post-silicon. We demonstrate the feasibility of this approach and summarize our findings based on the analysis of silicon speedpaths from a 65nm P4 microprocessor.

In modern high-performance microprocessors designed using advanced process technologies, the frequency of the part is often slower than what the static timing analysis tools predict before tape out. We give an overview of techniques used to observe the failing path on the tester, identify the dominant devices impacting the delay of the path, and learn from the failing path to fix other similar paths in the design. In particular, we describe a support vector machine based approach for learning from speedpaths observed in silicon.

For sub-65 nm design, there can be many timing effects not explicitly and/or accurately modeled and simulated. For design-silicon timing convergence, this paper describes a novel path-based diagnosis approach that analyzes and ranks potential design related issues causing the unexpected timing effects. We explain in detail how a path can be encoded with a set of diverse "features" based on one's knowledge of the potential issues. We explain how these features can be interpreted differently in a data learning algorithm based on adjusting a so-called kernel function. Then, we explain how kernel-based data learning can be used to rank the importance of features such that a feature contributing the most to design-silicon timing mismatch is ranked the highest. We conclude the paper by showing an application result on an industrial ASIC design.

In the post-silicon stage, timing information can be extracted from two sources: (1) on-chip monitors and (2) delay testing. In the past, delay test data has been overlooked in the correlation study. In this paper, we take path delay testing as an example to illustrate how test data can be incorporated in the overall design-silicon correlation effort. We describe a path-based methodology that correlates measured path delays from the good chips, to the path delays predicted by timing analysis. We discuss how statistical data mining can be employed for extracting information and show experimental results to demonstrate the potential of the proposed methodology.

As technology scales, it is becoming increasingly difficult for simulation and timing models to accurately predict silicon timing behavior. When a collection of chips fail in timing in a similar way, diagnosis and silicon debug look to find the root-causes for the failure. However, little work has been done to develop a methodology that looks for useful design information in the good-chip data. This paper describes a path-based methodology that correlates measured path delays from the good chips, to the path delays predicted by timing analysis. We explain how to utilize this methodology for evaluating the risk of timing modeling.