The paper presents the design and implementation of a dependability framework for a call-processing environment in a digital mobile telephone network controller. The framework contains a data audit subsystem to maintain the structural and semantic integrity of the database and a preemptive control flow checking technique, PECOS, to protect call-processing clients. Evaluation of the dependability-enhanced system is performed (using NFTAPE, a software-implemented error injection environment). The evaluation shows that for control flow errors in the client, the combination of PECOS and data audit eliminates fail-silence violations, reduces the incidence of client crashes, and eliminates client hangs. For database injections, data audit detects 85% of the errors and reduces the incidence of escaped errors. Evaluation of combined use of data and control checking (with error injection targeting the database and the client) shows coverage increase from 35% to 80% and indicates data flow errors as a key reason for error escapes.

Studies black box testing and verification of large systems. Testing data is collected from several test teams. A flat, integrated database of test, fault, repair, and source file information is built. A new analysis methodology based on the black box test design and white box analysis is proposed. The methodology is intended to support the reduction of testing costs and enhancement of software quality by improving test selection, eliminating test redundancy, and identifying error prone source files. Using example data from AT&T systems, the improved analysis methodology is demonstrated.>

A discussion is given on the use of software reliability models to guide engineering and management decisions on projects involving software. The focus is on experiences with using various software reliability models on actual projects, e.g. PBX project, space shuttle and software process control.>

The basic critical path tracing method for combinational circuits is outlined, and it is shown how it can produce pessimistic results in certain cases where fault effects propagate along multiple paths. The problem of extending the critical path tracing method to sequential circuits is considered. It is shown that the pessimistic nature of critical path tracing in combinational circuits may lead to optimistic results in sequential circuits, and a modification of the critical path tracing method to make it exact for combinational circuits is proposed. Based on this modification, a critical path tracing algorithm for synchronous sequential circuits is developed which is also exact.>

The author analyzes and models the software development process, and presents field experience for large distributed systems. Defect removal is shown to be the bottleneck in achieving the appropriate quality level before system deployment in the field. The time to defect detection, the defect repair time and a factor reflecting the introduction of new defects due to imperfect defect repair are some of the constants in the laws governing defect removal. Test coverage is a measure of defect removal effectiveness. A birth-death mathematical model based on these constants is developed and used to model field failure report data. The birth-death model is contrasted with a more classical decreasing exponential model. Both models indicate that defect removal is not a cost-effective way to achieve quality. As a result of the long latency of software defects in a system, defect prevention is suggested to be a far more practical solution to quality than defect removal.>

Critical path tracing has been shown to be faster than traditional fault simulation methods, but it produces pessimistic results in some cases involving reconvergent fanout. It is shown that the pessimistic nature of critical path tracing in combinational circuits can lead to incorrect results that are not necessarily pessimistic in sequential circuits. A modification of the method for removing the approximation is proposed, and a critical path tracing algorithm for synchronous sequential circuits is presented.>

Special-purpose CAD hardware is increasingly being considered as a means to meet the challenge posed to conventional (software-based) CAD tools by the growing complexity of VLSI circuits. In this paper we describe the architecture of a logic simulation machine employing distributed and parallel processing. Our architecture can accommodate different levels of modeling ranging from simple gates to complex functions, and support timing analysis. We estimate that simulation implemented by the proposed special-purpose hardware will be between 10 and 60 times faster than currently used software algorithms running on general-purpose computers. With the available technology, a throughput of 1 000 000 gate evaluations/sec can be achieved.

Special-purpose CAD hardware is increasingly being considered as a means to meet the challenge posed to conventional (software-based) CAD tools by the growing complexity of VLSI circuits. In this paper we describe the architecture of a logic simulation machine employing distributed and parallel processing. Our architecture can accommodate different levels of modeling ranging from simple gates to complex functions, and support timing analysis. We estimate that simulation implemented by the proposed special-purpose hardware will be between 10 and 60 times faster than currently used software algorithms running on general-purpose computers. With the available technology, a throughput of 1,000,000 gate evaluations/second can be achieved.

Special-purpose CAD hardware is increasingly being considered as a means to meet the challenge posed to conventional (software-based) CAD tools by the growing complexity of VLSI circuits. In this paper we describe the architecture of a logic simulation machine employing distributed and parallel processing. Our architecture can accommodate different levels of modeling ranging from simple gates to complex functions, and support timing analysis. We estimate that simulation implemented by the proposed special-purpose hardware will be between 10 and 60 times faster than currently used software algorithms running on general-purpose computers. With the available technology, a throughput of 1,000,000 gate evaluations/second can be achieved.

This paper proposes an extension of the D-algorithm to functions described in computer hardware description languages. The proposed extension is applicable to both procedural and nonprocedural languages. Methods of D-propagation through the basic constructs of these languages and test generation for circuits containing functions described in CHDL's are discussed. The fault modes considered are function variables stuck at 0 or 1, control faults, and function faults with user-specified faulty behaviors.