Pharmaceutical research. Weather prediction. Oil exploration. The data analysis demanded for these jobs can be awesome. As more applications are running on Linux clusters, there are a number of applications where job completion is critical. Today's jobs are getting longer and it's not unusual to come across jobs with run times that last for multiple days. As the number of nodes in a cluster expands, the likelihood that a job will be able to complete without a hardware related failure becomes statistically relevant. For an application like this, the cost of having the job fail and having to restart the job is enormous. You need efficient ways to help drive jobs to completion or be able to recover from failures.This session will review the importance of high availability functionality in high performance computing MPIs when running communication-intensive applications. Different approaches for cooperative and distributed check-point-restart will also be explored.

An early implementation of VIA over the latest I/O based SCI hardware is presented. SCI uses a shared address space model that in principle should fit well with the goals of the VIA API. This is demonstrated with a zerocopy and two one-copy implementations of the send/receive model. The paper shows that the VIA abstractions and provisions for zero-copy maps well to the SCI hardware. However, the results indicate that for small messages, a one-copy model outperforms the zero-copy model, due to the serializing properties of the VIA synchronization messages. In addition, a performance comparison is made with two other early VIA implementations: Berkeley’s VIA over Myrinet and VIA over GM. Results from these comparisons shows that a tuned host bridge is a necessity to exploit the hardware speed offered by these PCI 64bit 66MHz interconnects.

Two-level cache hierarchies will be a design issue in future high-performance CPUs. In this paper we evaluate various metrics for data cache* designs. We discuss both one- and two-level cache hierarchies. Our target is a new 100+ mips CPU, but the methods are applicable to any cache design. The basis of our work is a new trace-driven, multiprocess cache simulator. The simulator incorporates a simple priority-based scheduler which controls the execution of the processes. The scheduler blocks a process when a system call is executed. A workload consists of a total of 60 processes, distributed among seven unique programs with about nine instances each. We discuss two open bus systems supporting a coherent memory model, Futurebus+ and SCI, as the interconnect system for main memory.