Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Eric Schnarr

dblp:55/4809 · DBLP profile ↗
← Back
4ranked-venue papers
3as first author
0since 2021 · last 2001
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 3 · 2 first-authorSystems, architecture and hardware · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Performance modeling and evaluation · 92% Processor architecture and microarchitecture · 8%
Software engineering, system software, and programming languages
3 papers
Compilers and program optimization · 79% Program analysis · 21%

Topics — the 7 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Compilers and program optimization
partial evaluation
0.012001
Facile: A Language and Compiler for High-Performance Processor Simulators · PLDI 2001
Performance modeling and evaluation › simulation
architectural simulation
0.012001
Facile: A Language and Compiler for High-Performance Processor Simulators · PLDI 2001
Performance modeling and evaluation › simulation
processor simulation
0.011998
Fast Out-Of-Order Processor Simulation Using Memoization · ASPLOS 1998
Compilers and program optimization
instruction scheduling
0.011996
Instruction Scheduling and Executable Editing · MICRO 1996
Performance modeling and evaluation
profiling
0.011996
Instruction Scheduling and Executable Editing · MICRO 1996
Program analysis
binary analysis
0.011995
EEL: Machine-Independent Executable Editing · PLDI 1995
Processor architecture and microarchitecture
out-of-order execution
0.011998
Fast Out-Of-Order Processor Simulation Using Memoization · ASPLOS 1998

Methods — techniques the papers use, named apart from their topics

memoization · 0.1partial evaluation · 0.1local scheduling · 0.0speculative direct-execution · 0.0fast-forwarding · 0.0
YearPublicationVenuePosition
2001 Facile: A Language and Compiler for High-Performance Processor Simulators
abstract
Architectural simulators are essential tools for computer architecture and systems research and development. Simulators, however, are becoming frustratingly slow, because they must now model increasingly complex micro-architectures running realistic workloads. Previously, we developed a technique called fast-forwarding, which applied partial evaluation and mermoization to improve the performance of detailed architectural simulations by as much as an order of magnitude [14].
Eric Schnarr, Mark D. Hill, James R. Larus
PLDI1
1998 Fast Out-Of-Order Processor Simulation Using Memoization
abstract
Our new out-of-order processor simulatol; FastSim, uses two innovations to speed up simulation 8--15 times (vs. Wisconsin SimpleScalar) with no loss in simulation accuracy. First, FastSim uses speculative direct-execution to accelerate the functional emulation of speculatively executed program code. Second, it uses a variation on memoization---a well-known technique in programming language implementation---to cache microarchitecture states and the resulting simulator actions, and then "fast forwards" the simulation the next time a cached state is reached. Fast-forwarding accelerates simulation by an order of magnitude, while producing exactly the same, cycle-accurate result as conventional simulation.
Eric Schnarr, James R. Larus
ASPLOS1
1996 Instruction Scheduling and Executable Editing
abstract
Modern microprocessors offer more instruction-level parallelism than most programs and compilers can currently exploit. The resulting disparity between a machine's peak and actual performance, while frustrating for computer architects and chip manufacturers, opens the exciting possibility of low-cost instrumentation for measurement, simulation, or emulation. Instrumentation code that executes in previously unused processor cycles is effectively hidden. On two superscalar SPARC processors, a simple, local scheduler hid an average of 13% of the overhead cost of profiling instrumentation in the SPECINT benchmarks and an average of 33% of the profiling cost in the SPECFP benchmarks.
Eric Schnarr, James R. Larus
MICRO1
1995 EEL: Machine-Independent Executable Editing
abstract
EEL (Executable Editing Library) is a library for building tools to analyze and modify an executable (compiled) program. The systems and languages communities have built many tools for error detection, fault isolation, architecture translation, performance measurement, simulation, and optimization using this approach of modifying executables. Currently, however, tools of this sort are difficult and time-consuming to write and are usually closely tied to a particular machine and operating system. EEL supports a machine- and system-independent editing model that enables tool builders to modify an executable without being aware of the details of the underlying architecture or operating system or being concerned with the consequences of deleting instructions or adding foreign code.
James R. Larus, Eric Schnarr
PLDI2