This paper presents a compilation procedure for synthesizing multi-clock SVA properties for formal verification. The synthesis framework is built upon an existing compilation algorithm for single-clock SVA properties. While we could use the SVA rewriting rules to transform a multi-clock property into a single-clocked property and then apply existing techniques, instead we propose techniques to selectively model the multi-clock operators to produce a smaller checker logic. Through recursive construction and syntactic transformation, we are able demonstrate the efficiency of the technique and the generated checker logic is provably equivalent to the rewritten version.

This paper describes techniques for efficiently handling a subset of System Verilog Assertion(SVA) safety properties with local variables in formal verification. The techniques produce checker circuits using datapath logic and pipeline registers for handling the local variables where the datapath logic and pipeline registers scales lineally to the size of the property expressed in the SVA abstract grammar.

A RTL C-Based design and verification methodology is presented with enabled the successful high speed validation of a 7 million gate simultaneous multi-threaded (SMT) network processor. The methodology is centered on statically scheduled C-based coding style, C to HDL translation, and a novel RTL-C to RTL-Verilog equivalence checking flow. It leverages improved simulation performance combined with static techniques to reduce the amount of RTL-Verilog and gate-level verification required during development.

Abstract- This paper describes methods for partitioning and optimizing controllers described by hierarchical high-level descriptions. The methods utilize the structure of the high-level description, provide flexible exploration of the trade-off between combinational logic and registers to reduce implementation cost, and allow the designer to control the synthesis process. Results are presented using industrial examples. 1.

This paper describes an automated design andsynthesis methodology for telecommunications ASIC's.Array frames, an array structured visualization of theprocessing problem, are used in the specification anddebugging of the design. This allows design much closer to thespecification level. The array frame concept is integratedinto the Dali structured control logic design environment. AnSDH (Synchronous Digital Hierarchy) style exampledemon-strates the use of array frames. The array frame approachwas successfully applied in industrial applications.

This paper describes a new high-level synthesis system based on the hierarchical production based specification (PBS). Advantages of this form of specification are that the designer does not describe the control flow in terms of explicit states or control variables, and that the designer does not describe a particular form of implementation. The production-based specification also separates the specification of the control aspects and data-flow aspects of the design. The control is implicitly described via the production hierarchy, while the data-flow is described as action computations. This approach is a hardware analog of popular software engineering techniques. The Clairvoyant system automatically constructs a controlling machine from the PBS and this process is not impacted by the possibly exponentially larger deterministic state space of the designs. The encodings generated by the constructions compare favorably to encodings derived using graph-based state encoding techniques in terms of logic complexity and logic depth. These construction techniques utilize recent advances in BDD techniques.>

Article High-level symbolic construction technique for high performance sequential synthesis Share on Authors: Andrew Seawright View Profile , Forrest Brewer View Profile Authors Info & Claims DAC '93: Proceedings of the 30th international Design Automation ConferenceJuly 1993 Pages 424–428https://doi.org/10.1145/157485.164961Online:01 July 1993Publication History 15citation193DownloadsMetricsTotal Citations15Total Downloads193Last 12 Months1Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

The authors present a novel decomposition of the high-level data-path synthesis problem taking as input scheduled procedural behavior and outputting geometrically placed and optimized linear data-paths. The technique uses communication based analysis to allow simultaneous synthesis of the placement, bindings, and RTL topology for high performance linear data-paths. In effect, the procedure creates an architecture and a layout with specified performance and cost constraints.>

This paper addresses relevant issues in connectivity synthesis particularly with respect to other design concerns in high-level behavioral synthesis.A restricted model is used to run a series of design experimerus to provide insight into the relationship between scheduling, conrwctivity, and placement & routing.Contrary to the common approach of counting multiplexer, multiplexer inputs, and busses, this approach looks at more germanz issues, namely: I) How to decide how much a "bus" is really going to cost, 2) How much does "load balanced" scheduling help, especially in the case of resource constrained scheduling, and 3) Should the number of multiplexer inputs really be the main criterion for judging the connectivity quality of the designs?