A 14GHz CML-based phase interpolator (PI) is proposed for a 4-way time-interleaved 56Gbaud clock and data recovery (CDR). The phase interpolator has a resolution of 7 bits and is implemented in 28 nm CMOS technology with a 1.0V power supply. The proposed PI consists of a PI controller, a slew-rate-control buffer, and a phase mixer. The distribution of the tail current sources, short-channel effect, and the slew rate of the input signals are analyzed and several methods are proposed to optimize the interpolation linearity. The measured integral non-linearity (INL) and the calculated differential non-linearity (DNL) are less than 1.20 LSB and 0.27 LSB respectively at 14GHz. The total power consumption is 8.48mW.

In this paper, a 2-bit 4-level 4-wire (2B4L4W) signaling scheme is proposed, which maps two bits of information to four values distributed over four wires. The signaling scheme makes two wires transfer identical data and complementary data alternately, causing identical single-ended inter-symbol interference (ISI) at both pre- and post-cursor with an odd number cursor index. More than half the amount of total ISI is eliminated without equalizers or adaption logic. The proposed scheme doesn't incorporate the feedback loop, which allows for higher operating speed. A prototype transceiver is designed in 14nm FinFET process. The post-layout simulation results indicate that the transceiver is capable of operating at 56Gb/s over an 8.4dB-loss channel. The total power efficiency is 2.72 pJ/b.

A 25Gb/s PAM-4 receiver is presented with 4- tap adaptive DFE and sampling clock optimization. PAM-4 signaling suffers more from non-optimal sampling clock phase which degrades BER. By finding the point with the least pre-cursor ISI, the sampling clock can be recovered with optimal phase, which improves the BER by as much as 109through 12.5dB channel loss. A novel clocked amplifier is implemented as a slicer to reduce the loop delay and meet the timing constraints of the direct feedback. Fabricated in 55nm CMOS technology, the receiver occupies 0.27mm2and consumes 185mW at 25Gb/s with a power supply of 1.2V.

A 14GHz digitally controlled oscillator (DCO) is proposed for all-digital phase-locked loop (ADPLL). With a cascade differential-capacitor array, the resolution of DCO is enhanced, which leads to a decrease in quantization noise, while area cost and substrate noise are also significantly reduced. In addition, a resistor-biased DCO output buffer is used to cut down phase noise by eliminating flicker and thermal noise conventional current-mirror structure brings. The proposed DCO is designed in 14nm FinFET process, achieving a phase noise of -110dBc/Hz at 1MHz offset and a frequency resolution of 7kHz. DCO operates in a frequency range of 17.8%, with a 0.017 mm2core area. The DCO consumes 6.3mW from a 0.8V supply voltage.

A novel structure of analog signal processing circuits for coherent receivers is proposed and implemented in 28-nm CMOS technology with 1V supply voltage in this work. To avoid excessive taps in equalizer or prolix circuit modules, the system combines the crosstalk equalizer and carrier phase recovery circuits with the application of 2 kinds of multipliers to compensate linearity for higher accuracy. In order to achieve stronger converging ability, simplify the system realization and further reduce power dissipation, the chromatic dispersion equalizer uses DFE instead of FFE to eliminate post cursor. Simulation results show circuits are capable of equalizing signals of 40-ps/nm chromatic dispersion effect, 300-kHz dynamic polarization crosstalk and 100MHz frequency offset with power of 1.2 Watt.

A double-comparison capacitive digital-to-analog converter (CDAC) settling error correction scheme for binary scaled successive approximation register (SAR) analog-to-digital converters (ADCs) is proposed in this paper. In the proposed scheme, two comparators make their decisions sequentially within each conversion cycle to guarantee the correctness of the decisions, while allowing the CDAC settling overlap with comparator and logic operations. Compared to conventional settling error correction techniques, the proposed scheme potentially relaxes the settling requirement without additional capacitors and extra conversion cycles. The effectiveness of the scheme is verified by a 500MS/s 8-bit SAR ADC in 55 nm CMOS technology. The settling time for the maximum possible voltage shift is reduced by 72%. The ADC core occupies 0.017mm2and consumes 2.69mW from 1.2V supply. The proposed ADC achieves an averaged 45.8dB SNDR in the first Nyquist zone which indicates an improvement of 3dB compared to conventional ADC.

An ultra-low phase error, low power Quadrature Clock Generator (QCG) based on two-stage Poly Phase Filter (PPF) with intermediate point compensation is proposed. With the incorporation of a RC sensing network to detect the process variation, the PPF compensates its quadrature phase error by feeding the network's output to the intermediate point. Meanwhile, output amplitude of the PPF is enhanced as a benefit of intermediate point utilization. In comparison with conventional Type-I and Type-II PPF-based QCGs, the proposed one excels in broadband phase error as a result of lowest phase/amplitude error combination in a typical process variation scenario (ΔR=±20%, ΔC=±10%). Furthermore, it stands out in power consumption performance due to its amplitude enhancement, which effectively reduces the amplification power passive PPF implementations always need. The phase error of proposed QCG is less than 0.32° at 10GHz, and no more than 0.92 ° over 8GHz-12GHz with process variations in Global Foundry 55nm CMOS process. The QCG consumes 9.6mW from a 1.2V supply voltage.

A novel ΔΣ time-to-digital converter (TDC) with a time mode accumulator and a multi-bit quantizer is proposed in this work. Measurement time is reduced when compared with single-bit ΔΣ TDCs. A time difference adder consisting of gated delay-line based time-registers is used to serve as the time accumulator. A dynamic element matching algorithm is implemented to mitigate the performance loss degraded by the non-linearity of the multi-bit quantizer. The TDC is designed and simulated using a 65nm CMOS process and operates at a 100MHz sampling rate. For a 1.25MHz bandwidth, 108fsrmsintegrated noise or 2.4ps equivalent resolution is achieved. The power consumption is only 0.45 mW and the figure of merit (FoM) is calculated to be 154fJ/step.

A 10 GHz bang-bang all-digital phase-locked loop (BB-ADPLL) is proposed for high-speed wireline communication. A novel high resolution fractional capacitor is proposed in LC-DCO, which overcomes the process limitation of MOM capacitors and raises Q factor. The resolution of DCO is improved more than ten times and the Q factor of the LC-tank increases two times. The ADPLL is fabricated in 65 nm CMOS process. The phase noise of the proposed 10 GHz ADPLL is -95.7 dBc/Hz @ 1 MHz offset and the RMS jitter is 0.88 ps (1 kHz to 100 MHz). The ADPLL consumes 10.5 mW from a 1.2 V supply voltage and occupies an active area of 0.06 mm2.

The proposed time-voltage-time convertor (TVTC) based quadrature clock generator (QCG) utilizes digitally controlled delay line (DCDL) and phase mixer to generate four-phase clock and a feedback path to detect the difference in amplitudes of the four-phase clocks. By adjusting the DCDL adaptively, the QCG gives quadrature clock with ultra-low phase error. TVTC can improve the effective resolution of the DCDL by 3.66 times without degrading the tuning range of the DCDL, which ranges from 8.52 GHz to 11.34 GHz. With the help of TVTC, the phase error of the quadrature clock is reduced by 82% compared with DLL's. The proposed QCG reduces the use of supply-sensitive DCDL, which reduces the supply noise by 75.1%. The QCG is designed in 65 nm CMOS process. The phase error of the proposed QCG is 0.34° @ 10 GHz. The QCG consumes 12.7 mW from a 1.2 V supply voltage.

A 40 Gb/s PAM4 receiver with novel digital clock and data recovery (CDR) and one tap decision feedback equalizer (DFE) has been presented. Without sophisticated transition detection and selection modules, the proposed CDR utilizes three bang-bang phase detectors sampling all the transitions to detect the phase error between the data and clock, achieving larger transition density and CDR bandwidth. Eight interleaved 5 GHz clocks with sense amplifiers are utilized to sample the data and edge, decreasing the power consumption of DFE. Two serial sense amplifiers are used to improve the gain, while two sets of phase interpolators are implemented to reduce the delay of the DFE loop. The 40 Gb/s PAM4 receiver is realized in 65nm CMOS technology. It provides as much as 16.7 dB equalization with linear equalizer and DFE. The overall power consumption is 74.9 mW at 1.2V supply, achieving a power efficiency of 1.87pJ/bit.

A high-speed low-power 1:16 demultiplexer with a novel symmetrical-edge-delay sense amplifier is presented in this paper. The traditional Sense-Amplifier-Based Flip-Flop (SAFF) has asymmetric rising and falling edges with the fact that the falling edge lags the rising edge the time of a gate delay, which has become a bottleneck of speed. In order to overcome the problem of nonsymmetry of output data edges caused by the set-reset (SR) latch in the Sense-Amplifier-Based Flip-Flop, a new slave latch controlled by the clock is proposed which reduces delay and improves sensitivity considerably. A new type of CMOS logic 2:16 DEMUX is also proposed which can save about 20% area and 15% power consumption compared with the conventional structure. The power consumption of DEMUX is only 0.36mW at the date rate of 10Gb/s and 1.27mW at 20Gb/s. The proposed structure is based on Global Foundry 65nm CMOS process.

A novel PAM4 receiver with adaptive threshold voltage, adaptive decision feedback equalizer and fixed linear equalizer has been presented. The proposed techniques enable threshold voltage to be adjusted automatically depending on data rate, signal swing and loss of channel. Consequently the receiver can be used in various situations without being manually calibrated. Adaptive decision feedback equalizer for PAM4 signaling is proposed, incorporated with sign-sign least mean square algorithm. Simulation results across lossy channel show proper convergence of threshold voltage and decision feedback equalizer values with the proposed receiver.

A novel half-rate source-series-terminated (SST) transmitter in 65nm bulk CMOS technology is presented in this paper. Compared to previous half-rate SST transmitters, the proposed one consists of four binary-weighted slices increasing proportionally as 1x, 2x, 4x and 8x and the range of pre-emphasis level is increased greatly by the clock-match block to adapt to different channel. The half-rate transmitter can adjust the pre-emphasis level from 1.2dB to 23dB. The transmitter output impedance is adjustable from 33ohms to 64ohms. A power consumption of 24mW is measured at a transmit rate of 6 GB/s which is power-efficient compared to previous half-rate SST transmitter.

This paper presents a 2-tap 40-Gb/s 4-PAM transmitter with level selection based pre-emphasis. The parallel input to the transmitter is pre-coded at low frequencies, so that the pre-emphasis tap injects different currents into the output node of the transmitter based on different level changes of the output signal. The proposed pre-emphasis suppresses overshooting and lowers power consumption. The test chip is fabricated in a SMIC 65-nm CMOS process and shows a 45.2 mW power dissipation while operating at 20-GS/s, which is equivalent to 40-Gb/s.

A method to reduce the supply voltage sensitivity of digitally-controlled ring oscillators (DCROs) using digital current-regulated tuning is presented. By regulating the supply current of ring oscillator instead of its supply voltage, the proposed technique overcomes the limitations of conventional voltage regulator, achieves high supply-noise rejection performance and digital tuning of current-regulated DCRO. The proposed DCRO system implemented in a 0.13-μm CMOS process operates from 1.8 to 3.7 GHz. At 2.7 GHz, the current-regulated DCRO achieves static and dynamic supply-noise immunity of 0.0006%-fOUT/1%-VDDand 0.0014%-fOUT/1%-VDDrespectively, while employing a 150-pF decoupling capacitor, and consuming 1.7 mW from a 1.2 V supply.

A novel frequency search algorithm is proposed in this paper to achieve fast locking in all digital PLL (ADPLL) with no phase tracking being required. According to phase and frequency error, the normalized tuning word (NTW) is calculated so that the output frequency reaches the desired frequency immediately. As the non-idealities, such as DCO gain estimation error and TDC finite resolution, greatly affect the accuracy of the calculation, the output frequency is continuously measured and frequency error is averaged to minimize those impacts. With 0.13um CMOS process, the proposed ADPLL operates at 2.7 GHz and achieves 0.35 us locking time while consuming 7.47mW.

This paper examines two kinds of bang-bang semidigital dual loop CDR architectures: 2nd-order and 3rd-order. Quantitative analysis is made in detail between the two in the presence of spread spectrum clocking (SSC) which hasn't been well studied. Moreover, a novel SSC estimator based on 3rd-order architecture is proposed to suppress the frequency-overshoot of conventional 3rd-order CDR happening at the switching points of SSC. The depth of its SSC tracking may be up to 10000ppm at 30 KHz which helps to reduce EMI.

As network data rate increases rapidly, high-speed signaling circuits for server communication pose many design challenges due to various system requirements using different interconnect mediums. This paper discusses main problems and solutions of high-speed circuits for server interconnect. Then, it presents a high-speed circuit implementation for such interconnect using 90nm CMOS technology that achieved data rate at 6.25 Gbps in a backplane environment.