Quantized Neural Networks (QNNs) are widely deployed in safety-critical edge applications. In this regard, understanding the severity and mechanisms of security threats is essential for safeguarding the systems during deployment. This paper presents Multi-Target Bit Trojan (MTBT), the first bit-flip backdoor attack capable of simultaneously hijacking multiple target classes through minimal weight modifications. Unlike prior work that targets a single class, MTBT jointly optimizes trigger generation and weight perturbations to enable multi-target attacks with a single Trojan in CNN models. Our evaluation on an 8-bit quantized ResNet-18 demonstrates that MTBT achieves over 95% Attack Success Rate (ASR) for two target classes with only 55 bit-flips, with a minimal impact on the baseline accuracy. Furthermore, MTBT successfully scales to three simultaneous targets, achieving a mean ASR exceeding 85% across all classes in CIFAR-10.

RISC-V processors are becoming ubiquitous in critical applications, but their susceptibility to microarchitectural side-channel attacks is a serious concern. Detection of microarchitectural attacks in RISC-V is an emerging research topic that is relatively underexplored, compared to x86 and ARM. The first line of work to detect flush+fault-based microarchitectural attacks in RISC-V leverages Machine Learning (ML) models, yet it leaves several practical aspects that need further investigation. To address overlooked issues, we leveraged gem5 and propose a new detection method combining statistical preprocessing and association rule mining having reconfiguration capabilities to generalize the detection method for any microarchitectural attack. The performance comparison with state-of-the-art reveals that the proposed detection method achieves up to 5.15% increase in accuracy, 7% rise in precision, and 3.91% improvement in recall under the cryptographic, computational, and memory-intensive workloads alongside its flexibility to detect new variant of flush+fault attack. Moreover, as the attack detection relies on association rules, their human-interpretable nature provides deep insight to understand microarchitectural behavior during the execution of attack and benign applications.

The IEEE European Test Symposium (ETS) has been facilitating progress in electronic systems testing since its launch in 1996. On the occasion of its 30th anniversary, this collaborative paper gathers sections by 21 ETS teams to outline their influential ideas and milestones. Each team’s section highlights historical perspective, current research, frameworks and projects as well as forward-looking research agendas in the area of electronic-based circuits and systems testing, reliability, safety, security and validation. This anniversary summary documents how research of various ETS teams, exemplifying the test community, has been evolving and transitioning from concepts to practical standards and Electronic Design Automation (EDA) tools and flows. This legacy is a strong base to drive the next generation of advances in electronic systems testing.

Autonomous driving (AD) system designers need methods to efficiently debug vulnerabilities found in control algorithms. Existing methods lack alignment to the requirements of AD control designers to provide an analysis of the parameters of the AD system and how they are affected by cyber-attacks. We introduce ADAssure, a methodology for debugging AD control system algorithms that incorporates automated mechanisms which support generation of assertions to guide the AD system designer to identify vulnerabilities in the system. Our evaluation of ADAssure on a real-world AD vehicular system using diverse cyber-attacks developed a set of assertions that identified weaknesses in the OpenPlanner 2.5 AD planning algorithm and its constituent planning functions. Working with an AD control system designer and safety validation engineer, the results of ADAssure identified remediation of the AD control system, which can support the implementation of a redundant observer for data integrity checking and improvements to the planning algorithm. The adoption of ADAssure improves autonomous system design by providing a systematic approach to enhance safety and reliability through the identification and mitigation of vulnerabilities from corner cases.

Systolic array has emerged as a prominent archi-tecture for Deep Neural Network (DNN) hardware accelerators, providing high-throughput and low-latency performance essen-tial for deploying DNNs across diverse applications. However, when used in safety-critical applications, reliability assessment is mandatory to guarantee the correct behavior of DNN accelerators. While fault injection stands out as a well-established practical and robust method for reliability assessment, it is still a very time-consuming process. This paper addresses the time efficiency issue by introducing a novel hierarchical software-based hardware-aware fault injection strategy tailored for systolic array-based DNN accelerators. The uniform Recurrent Equations system is used for software modeling of the systolic-array core of the DNN accelerators. The approach demonstrates a reduction of the fault injection time up to 3 × compared to the state-of-the-art hybrid (software/hardware) hardware-aware fault injection frameworks and more than 2000 × compared to RT-level fault injection frameworks - without compromising accuracy. Additionally, we propose and evaluate a new reliability metric through experimental assessment. The performance of the framework is studied on state-of-the-art DNN benchmarks.

Multiplication is the most resource-hungry operation in the neural network’s processing elements. In this paper, we propose an architecture of a novel adaptive fault-tolerant approximate multiplier tailored for ASIC-based DNN accelerators. AdAM employs an adaptive adder relying on an unconventional use of the leading one position value of the inputs for fault detection through the optimization of unutilized adder resources. The proposed architecture uses a lightweight fault mitigation technique that sets the detected faulty bits to zero. The hardware resource utilization and the DNN accelerator’s reliability metrics are used to compare the proposed solution against the triple modular redundancy (TMR) in multiplication, unprotected exact multiplication, and unprotected approximate multiplication. It is demonstrated that the proposed architecture enables a multiplication with a reliability level close to the multipliers protected by TMR utilizing 63.54% less area and having 39.06% lower power-delay product compared to the exact multiplier.

Convolutional Neural Networks (CNNs) have become integral in safety-critical applications, thus raising concerns about their fault tolerance. Conventional hardwaredependent fault tolerance methods, such as Triple Modular Redundancy (TMR), are computationally expensive, imposing a remarkable overhead on CNNs. Whereas fault tolerance techniques can be applied either at the hardware level or at the model levels, the latter provides more flexibility without sacrificing generality. This paper introduces a model-level hardening approach for CNNs by integrating error correction directly into the neural networks. The approach is hardwareagnostic and does not require any changes to the underlying accelerator device. Analyzing the vulnerability of parameters enables the duplication of selective filters/neurons so that their output channels are effectively corrected with an efficient and robust correction layer. The proposed method demonstrates fault resilience nearly equivalent to TMR-based correction but with significantly reduced overhead. Nevertheless, there exists an inherent overhead to the baseline CNNs. To tackle this issue, a cost-effective parameter vulnerability based pruning technique is proposed that outperforms the conventional pruning method, yielding smaller networks with a negligible accuracy loss. Remarkably, the hardened pruned CNNs perform up to $\mathbf{2 4 \%}$ faster than the hardened un-pruned ones.

Since Deep Neural Networks (DNNs) gracefully withstands approximation due to its inherent redundancy, Approximate Computing (AxC) can be applied to reduce power consumption and execution time. In the literature, several works adopted the AxC paradigm to DNNs in the form of quantization, precision reduction, pruning, and functional approximation. Despite the promising results demonstrated so far, most of the existing works have applied homogeneous AxC techniques, meaning that the same degree of approximation has been applied to the entire DNN. However, different DNN components (i.e., channels, filters, layers, neurons) have different resiliency levels. This paper presents a framework for applying heterogeneous AxC to DNN hardware accelerators. The framework is based on the identification of channel resilience and applying a tailored degree of approximation per channel. Preliminary results carried out on the LeNet-5 model show that by using the proposed framework it is possible to decrease resource utilization by 65.2% and power consumption by 53.4% at the cost of a marginal drop of accuracy from 98.87% to 98.03%.

Reliability assessment is mandatory to guarantee the correct behavior of Deep Neural Network (DNN) hardware accelerators in safety-critical applications. While fault injection stands out as a well-established, practical and robust method for reliability assessment, it is still a very time-consuming process. This paper contributes with three recipes for optimizing the efficiency of the reliability assessment: a) hybrid analytical and hierarchical FI-based reliability assessment for systolic-array-based DNN accelerators; b) mixing techniques for the reliability assessment of in-chip AI accelerators in GPUs; c) reliability assessment of DNN hardware accelerators through physical fault injection. The experimental results demonstrate the efficiency of the proposed methods applied to their target DNN HW accelerator platforms.

Nowadays, the extensive exploitation of Deep Neural Networks (DNNs) in safety-critical applications raises new reliability concerns. In practice, methods for fault injection by emulation in hardware are efficient and widely used to study the resilience of DNN architectures for mitigating reliability issues already at the early design stages. However, the state-of-the-art methods for fault injection by emulation incur a spectrum of time-, design-and control-complexity problems. To overcome these issues, a novel resiliency assessment method called APPRAISER is proposed that applies functional approximation for a non-conventional purpose and employs approximate computing errors for its interest. By adopting this concept in the resiliency assessment domain, APPRAISER provides thousands of times speed-up in the assessment process, while keeping high accuracy of the analysis. In this paper, APPRAISER is validated by comparing it with state-of-the-art approaches for fault injection by emulation in FPGA. By this, the feasibility of the idea is demonstrated, and a new perspective in resiliency evaluation for DNNs is opened.

Deep Neural Networks (DNNs) and their accelerators are being deployed ever more frequently in safety-critical applications leading to increasing reliability concerns. A traditional and accurate method for assessing DNNs’ reliability has been resorting to fault injection, which, however, suffers from prohibitive time complexity. While analytical and hybrid fault injection-/analytical-based methods have been proposed, they are either inaccurate or specific to particular accelerator architectures.In this work, we propose a novel accurate, fine-grain, metric-oriented, and accelerator-agnostic method called DeepVigor that provides vulnerability value ranges for DNN neurons’ outputs. An outcome of DeepVigor is an analytical model representing vulnerable and non-vulnerable ranges for each neuron that can be exploited to develop different techniques for improving DNNs’ reliability. Moreover, DeepVigor provides reliability assessment metrics based on vulnerability factors for bits, neurons, and layers using the vulnerability ranges.The proposed method is not only faster than fault injection but also provides extensive and accurate information about the reliability of DNNs, independent from the accelerator. The experimental evaluations in the paper indicate that the proposed vulnerability ranges are 99.9% to 100% accurate even when evaluated on previously unseen test data. Also, it is shown that the obtained vulnerability factors represent the criticality of bits, neurons, and layers proficiently. DeepVigor is implemented in the PyTorch framework and validated on complex DNN benchmarks.

The accelerated growth of computing systems' complexity makes comprehensive design verification challenging and time-consuming. In practice, hard-to-model complex environments are unfeasible to be simulated exhaustively within a reasonable time frame. Therefore, some corner-case conditions can be overlooked and design errors might escape to the final product. This means that it is imperative for the system to be able to detect and locate bugs to enable self-repair. This is particularly crucial during long-term remote missions in order to apply graceful degradation. This paper proposes a novel online design error localization methodology for microprocessors by immediate analysis of traced and buffered signals upon a failure detection event, using a pre-trained Neural Network (NN) and existing processor components, i.e. trace buffers and AI accelerators. An in-house Neural Architecture Search (NAS) framework is used to train a tailored Multi-Layer Perceptron (MLP) NN for error localization at the microprocessor module-level resolution. The proposed approach is validated by simulating a RISC-V implementation with different workload programs. It is demonstrated to be capable of localizing the microprocessor module of bug origin with 92.81% accuracy, on average.

Deep Learning, and in particular, Deep Neural Network (DNN) is nowadays widely used in many scenarios, including safety-critical applications such as autonomous driving. In this context, besides energy efficiency and performance, reliability plays a crucial role since a system failure can jeopardize human life. As with any other device, the reliability of hardware architectures running DNNs has to be evaluated, usually through costly fault injection campaigns. This paper explores approximation and fault resiliency of DNN accelerators. We propose to use approximate (AxC) arithmetic circuits to agilely emulate errors in hardware without performing fault injection on the DNN. To allow fast evaluation of AxC DNN, we developed an efficient GPU-based simulation framework. Further, we propose a fine-grain analysis of fault resiliency by examining fault propagation and masking in networks.

A digital finite impulse response (FIR) filter is a ubiquitous block in digital signal processing applications and its behavior is determined by its coefficients. To protect filter coefficients from an adversary, efficient obfuscation techniques have been proposed, either by hiding them behind decoys or replacing them by key bits. In this article, we initially introduce a query attack that can discover the secret key of such obfuscated FIR filters, which could not be broken by the existing prominent attacks. Then, we propose a first of its kind hybrid technique, including both hardware obfuscation and logic locking using a point function for the protection of parallel direct and transposed forms of digital FIR filters. Experimental results show that the hybrid protection technique can lead to FIR filters with higher security while maintaining the hardware complexity competitive or superior to those locked by prominent logic locking methods. It is also shown that the protected multiplier blocks and FIR filters are resilient to existing attacks. The results on different forms and realizations of FIR filters show that the parallel direct form FIR filter has a promising potential for a secure design.

Assertion-based verification is one of the viable solutions for the verification of computer systems. Assertions can be automatically generated by assertion miners however, these miners typically generate a high number of possibly redundant assertions. In turn, this results in higher costs and overheads in the verification process. Furthermore, these assertions have every so often low readability due to the high number of propositions that they contain. In this paper, an Innovative cost-effective Method for Minimizing assertion sets (IMMizer) has been proposed. IMMizer is performed by iden-tifying Contradictory Terms. These terms present the behaviors of the design under verification which are not specified by the initial assertion sets. Subsequently, a new assertion set is extracted based on the identified Contradictory Terms. Contrary to data-mining approaches that are unable to minimize the initial assertion set, but can only rank the set according to data-mining measurements, or mutant analysis approaches that require a long execution time, IMMizer is able to minimize the initial assertion set in a very short execution time. Experimental results showed that in the best case, this method has drastically reduced the number of assertions by 93% and the memory overhead imposed on the system by 87%, without any reduction in the detection of injected mutants.

Triple Modular Redundancy (TMR) is a well-known fault tolerance technique for avoiding errors in the Integrated Circuits (ICs) and it has been used in a wide range of applications. The TMR technique employs three instances of circuits realizing concurrently the same functionality whose outputs are compared through a majority voter. On the other hand, Side-Channel Attacks (SCAs) are powerful techniques to extract secret information from ICs based on the data collected from security critical operations. Over the years, the interplay between security and reliability is poorly studied. In this paper, we explore the performance of SCAs on the well-known Advanced Encryption Standard (AES) and its different realizations using the TMR technique. In this work, three implementations of the AES design under the TMR scheme are used and an SCA, which can collect power dissipation data from the physical netlist through simulations, is developed. The experimental results show that the TMR technique can increase the computation time of SCAs and more importantly, the use of functionally equivalent, but physically and structurally different instances in the TMR scheme can make it impossible for SCAs to discover the secret key.

Deep Learning (DL) algorithms have proved to be successful in various domains. Typically, the models use Floating Point (FP) numeric formats and are executed on Graphical Processing Units (GPUs). However, Field Programmable Gate Arrays (FPGAs) are more energy-efficient and, therefore, a better platform for resource-constrained devices. As the FP design infers many FPGA resources, it is replaced with quantized fixed-point implementations in state-of-the-art. The loss of precision is mitigated by dynamically adjusting the radix point on network layers, reconfiguration, and re-training. In this paper, we present the first Triple Fixed-Point (TFxP) architecture, which provides the computational precision of FP while using significantly fewer hardware resources and does not need network re-training. Based on a comparison of FP and existing Fixed-Point (FxP) implementations in combination with a detailed precision analysis of YOLOv2 weights and activation values, the novel TFxP format is introduced.

Cache logical side channel attacks pose a significant threat to the security of modern computer systems. This is a result of exploitation of cache information leakages arising from cache contention. Detection of such leakages can be inferred from cache behavior and processes' access patterns during run time. To achieve this, a detection template that uses available information on cache outputs and process accesses at run-time is required. In this work, such template is proposed and implemented as a hardware monitor called Cache Leakage Detector (CLD). CLD is a high-accuracy, cost-effective and scalable run-time cache information leakage detector. CLD uses cache signals and process IDs to detect exploitable cache access patterns. It does so by identifying potential information leakage patterns. Accuracy of CLD is evaluated by using several benchmarks and injecting attacks into a 128-bit key AES algorithm. The experiments demonstrate that CLD has far higher detection accuracy (0.7964 vs 0.3195) and lower percentage of false positive detections (1.2% vs 30.6%) compared to a state-of-the-art hardware detector. Moreover, CLD introduces a very low area overhead of 0.002% to the total area of the cache. Experimental result section reports the above claims in detail.

In this paper, a concept for generating tests for RISC processors is proposed relying solely on functional information such as the instruction set without any knowledge of the implementation details. For the first time, the effect-cause idea, instead of the traditional cause-effect fault driven approach, is applied for test generation. For implementing the effect-cause idea, a novel high-level constraint-based functional fault model is developed. This novelty made it possible to extend the classical Stuck-At Fault (SAF) model, applied so far in evaluating the quality of processor testing, not only to a large class of structural faults, such as conditional SAF, bridging faults, delay faults etc., but also to the functional faults similar to those covered by the March algorithm in memory testing. By experimental research it was demonstrated that the test quality of the proposed implementation-independent test generation method produces test sequences with comparable or better fault coverages for SAF and Transition Delay Faults (TDF) than known methods utilizing knowledge about the implementation details.

This paper presents a high-level circuit obfuscation technique to prevent the theft of intellectual property (IP) of integrated circuits. In particular, our technique protects a class of circuits that relies on constant multiplications, such as neural networks and filters, where the constants themselves are the IP to be protected. By making use of decoy constants and a key-based scheme, a reverse engineer adversary at an untrusted foundry is rendered incapable of discerning true constants from decoys. The time-multiplexed constant multiplication (TMCM) block of such circuits, which realizes the multiplication of an input variable by a constant at a time, is considered as our case study for obfuscation. Furthermore, two TMCM design architectures are taken into account; an implementation using a multiplier and a multiplierless shift-adds implementation. Optimization methods are also applied to reduce the hardware complexity of these architectures. The well-known satisfiability (SAT) and automatic test pattern generation (ATPG) based attacks are used to determine the vulnerability of the obfuscated designs. It is observed that the proposed technique incurs small overheads in area, power, and delay that are comparable to the hardware complexity of prominent logic locking methods. Yet, the advantage of our approach is in the insight that constants - instead of arbitrary circuit nodes - become key-protected.

The recent trends for nanoelectronic computing systems include machine-to-machine communication in the era of Internet-of-Things (IoT) and autonomous systems, complex safety-critical applications, extreme miniaturization of implementation technologies and intensive interaction with the physical world. These set tough requirements on mutually dependent extra-functional design aspects. The H2020 MSCAITN project RESCUE is focused on key challenges for reliability, security and quality, as well as related electronic design automation tools and methodologies. The objectives include both research advancements and cross-sectoral training of a new generation of interdisciplinary researchers. Notable interdisciplinary collaborative research results for the first halfperiod include novel approaches for test generation, soft-error and transient faults vulnerability analysis, cross-layer fault-tolerance and error-resilience, functional safety validation, reliability assessment and run-time management, HW security enhancement and initial implementation of these into holistic EDA tools.

In the recent years, cache based side-channel attacks have become a serious threat for computers. To face this issue, researches have been looking at verifying the security policies. However, these approaches are limited to manual security verification and they typically work for a small subset of the attacks. Hence, an effective verification environment to automatically verify the cache security for all side-channel attacks is still missing. To address this shortcoming, we propose a security verification methodology that formally verifies cache designs against cache side-channel vulnerabilities. Results show that this verification template is a straightforward, automated method in verifying cache invulnerability.

We propose a method for synthesis of Software-Based Self-Test (SBST) for testing RISC type of microprocessors without needing the knowledge of implementation details. The test covers a large class of faults and a special target is to detect Transition Delay Faults (TDF). To reduce the complexity, the processor is partitioned into Modules Under Test (MUT), and each MUT is in turn partitioned into data and control parts. For the data parts, pseudo-exhaustive tests are applied, whereas for the control parts a novel functional control fault model was developed. The test is regular, represented in a compact form allowing easy unrolling during test execution. Experimental results demonstrate high Stuck-At Fault (SAF) and TDF coverage, despite the lack of knowledge of implementation details.

Self-healing is a promising approach for designing reliable digital systems. It refers to the ability of a system to detect faults and automatically fixing them to avoid total failure. With the development of digital systems, heterogeneous systems, in which some parts of the system are executed on the programmable logic, and some other parts run on the processing elements (CPU), are becoming more prevalent. In this work, we propose an adjustable self-healing method that is applicable to heterogeneous systems with accelerated functions and enables the designers to add the self-healing feature to the design. In this method, by manipulating the software codes that are being executed on the processing element, we add the ability to verify the accelerated functions on the programmable logic and heal the possible failures to the system. This is done not only in a straightforward manner but also without being forced to choose a specific reliability-overhead point. The designer will have the option to select the optimum configuration for a desired reliability level. Experimental results on a large design including several accelerated functions are provided and show 42% improvement of reliability by having 27% overhead, as an example of the reliability-overhead point.

Interest in memory systems' security has increased during the last decade due to their vulnerabilities to be exploited by logical side channels attacks. A promising approach for attack detection at run-time is to monitor the cache memory's behavior. However, designing an environment capable of detecting and mitigating these attacks is very challenging. In current monitoring systems, attack mitigation has been largely neglected. To overcome these shortcomings, in this work, we present a secure cache called SCAAT. SCAAT is equipped with an attack mitigation system to handle attacks by remapping where data is stored in the cache to random locations. In addition, SCAAT uses an attack monitor that identifies suspicious behavior that indicates cache logical side-channel attacks. The effectiveness of SCAAT is analyzed and evaluated for several cache configurations in terms of area overhead and performance.

Cache attacks are one of the most wide-spread and dangerous threats to embedded computing systems' security. A promising approach to detect such attacks at runtime is to monitor the System-on-Chip (SoC) behavior. However, designing a secure SoC capable of detecting such attacks is very challenging: the monitors should be lightweight in order to avoid excessive power/energy and area costs and the attack behavior should be clearly known upfront. In this work, we present LiD-CAT, a lightweight and flexible hardware detector that is aware of leakage patterns that can be used by attackers to perform cache based attacks. LiD-CAT is a cache wrapper that implements a set of leakage properties derived from cache attacks and cache models using templates. These templates identify suspicious behavior that may lead to cache attacks. LiD-CAT is evaluated using two different cache architectures, one with a secure cache and one without. On each of them, SPEC2000 benchmarks are run together with malicious applications that execute cache attacks (i.e., Evict+Time, Prime+Probe, Flush+Reload and Flush+Flush). Results show that our lightweight detector successfully detects 99.99% of the attacks with less than 1% false-positives, has no timing penalties, and increases the area of a SoC with only 1.6%.

Deep learning neural networks have gained much attention in recent research. Excellent results in various domains have proved the usefulness of such algorithms. However, training a deep learning network requires substantial computational effort; therefore, resource-constrained systems like edge devices in the IoT domain still lack full implementations, and training of the network is offloaded to the cloud. Online or unsupervised training of the network, on the other hand, is often a must if the system has to adjust to possible drift of the environment parameters or there is not enough data available initially. This paper proposes the first Xilinx Zynq FPGA (Field Programmable Gate Array) based implementation of the contractive autoencoder (CAE), including training of the network.

The identification of safe faults (i.e., faults which are guaranteed not to produce any failure) in an electronic system is a crucial step when analyzing its dependability and its test plan development. Unfortunately, safe fault identification is poorly supported by available EDA tools, and thus remains an open problem. The complexity growth of modern systems used in safety-critical applications further complicates their identification. In this article, we identify some classes of safe faults within an embedded system based on a pipelined processor. A new method for automating the safe fault identification is also proposed. The safe faults belonging to each class are identified resorting to Automatic Test Pattern Generation (ATPG) techniques. The proposed methodology is applied to a sample system built around the OpenRisc1200 open source processor.

Current embedded systems are increasingly using networks, be it for connecting different components or in form of Network on Chips in case of Multi-Processor System on Chip. Knowing the performance parameters of those networks, especially in case that parts of the network are damaged, is the key to allow reliable behavior of the system. In this paper, we present an approach for measuring the performance parameters of embedded networks under different load and fault scenarios. First, the performance parameters of the network are measured in the nominal case. This information is then used to create a model of the network. For this model we provide a simulation environment, which injects faults into the network to evaluate the network under failure scenarios. We evaluated our approach on a Network on Chip consisting of 16 nodes arranged in a 4×4 matrix. Our evaluation shows that our approach can evaluate the fault effects in the network with good quality.

Recent safety standards set stringent requirements for the target fault coverage in embedded microprocessors, with the objective to guarantee robustness and functional safety of the critical electronic systems. This motivates the need for improving the quality of test generation for microprocessors. A new high-level implementation-independent test generation method for RISC processors is proposed. The set of instructions of the processor is partitioned into groups. For each group, a dedicated test template is created, to be used for generating two test programs, for testing the control and the data paths respectively. For testing the control part, a novel high-level control fault model is proposed. Using this model, a set of deterministic test data operands are generated for each instruction of the given group. The advantage of the high-level fault model is that it covers larger than SAF fault class including multiple fault coverage in the control part. For generating the data path test, pseudo-exhaustive data operands are used. We investigated the feasibility of the approach and demonstrated high efficiency of the generated test programs for testing the execute module of the miniMIPS RISC processor.

We present a three-step flow to improve Assertion-based Verification methodology with integrated RTL-to-TLM abstraction: First, an automatic assertion miner generates a large set of possible assertions from an RTL design. Second, automatic assertion qualification identifies the most interesting assertions from this set. Third, the assertions are abstracted to the transaction level, such that they can be re-used in TLM verification. We show that the proposed flow automatically chooses the best assertions among the ones generated to verify the design components when abstracted from RTL to TLM. Our experimental results indicate that the proposed methodology allows us to re-use the most interesting set at TLM without relying on any time consuming or error-prone manual transformations with a considerable amount of speed up and considerable reduction in the execution time.

This work proposes a fault injection methodology where Hardware Description Language (HDL) code slicing is exploited to prune fault injection locations, thus enabling more efficient campaigns for safety mechanisms evaluation. In particular, the dynamic HDL slicing technique provides for a highly collapsed critical fault list and allows avoiding injections at redundant locations or time-steps. Experimental results show that the proposed methodology integrated into commercial tool flow doubles the simulation speed when comparing to the state-of-the-art industrial-grade EDA tool flows.

The extreme complexity of digital systems enabled by nanometer-scale implementation technologies comes along with strengthened design requirements that are difficult to achieve with the conventional techniques. Over-designing beyond the minimal required guarantees may have negative impacts on the overall system's cost. In this paper we focus on the task of timing-critical logic paths identification in digital systems that has many applications in design and test field, like verifying the timing constraints of designs, estimating critical delays, Simulating path delay faults and reliability analysis such as ageing. The contribution is a new scalable simulation-based hierarchical search method for application-specific online-viable true critical paths identification in sequential circuits. The approach is motivated by the concept of mixed-critical systems, but it can be applied for any type of digital system. We propose to represent the circuits hierarchically at the level of higher level submodules using t e theory of Structurally Synthesized BDDs (SSBDD). The search space is limited by the application-specific context that enables accurate results even for complex sequential circuits. Experimental results demonstrate efficiency of the proposed approach, and considerable reduction of the length of critical paths if the application-specific constraints are taken into account.

A large number of crypto accelerators are being deployed with the widespread adoption of IoT. It is vitally important that these accelerators and other security hardware IPs are provably secure. Security is an extra functional requirement and hence many security verification tools are not mature. We propose an approach/flow - PASCAL - that works on RTL designs and discovers potential Timing Side Channel Attack (SCA) vulnerabilities in them. Based on information flow analysis, this is able to identify Timing Disparate Security Paths that could lead to information leakage. This flow also (automatically) eliminates the information leakage caused by the timing channel. The insertion of a lightweight Compensator Block as balancing or compliance FSM removes the timing channel with minimum modifications to the design with no impact on the clock cycle time or combinational delay of the critical path in the circuit.

This paper is dedicated to the IEEE European Test Symposium (ETS). It offers an overview of all the European Test Workshop and Symposium events, from its first edition in 1996 to the next edition in 2020.

Several approaches exist for specification mining of hardware designs, both at the RTL and system levels (e.g, TLM). These approaches mine assertions that specify the behavior of the design. Some of the techniques require the source code itself while others can extract assertions directly from simulation traces. The performance of some approaches is highly dependent on the number of simulation traces/use cases while there exist approaches which can extract assertions from a limited number of simulation traces. Apart from this aspect, the core of each assertion miner is different from the other ones. Some use expression templates to define assertions while some are based on the static analysis or information flow analysis. Unfortunately, it has been rarely considered which of the current approaches are more effective in describing functionality of particular types of designs. Thus, in this work, we analyze assertion miners which are template based and dynamic dependency graph based, respectively. We generate assertions from both approaches. The evaluation considers fault analysis on both assertion sets of extracted assertions. Moreover, both sets are combined and fault analysis has been applied on them. Experimental results show that each set approximately detects the same number of faults while when the two sets are combined the number of detected faults increases. Finally, a new, more efficient architecture for an effective assertion miner has been developed based on the study in this work.

We propose a generic strategy for formalized synthesis of Software-Based Self-Test (SBST) for testing microprocessors with RISC architecture with the goal to achieve high gate-level fault coverage without knowing the gate-level implementation detail, and to have well-structured compact test, which can be easily unrolled on-line during test execution. The high-level model of the microprocessor is derived from the instruction set and from the architectural features introduced for increasing performance, like pipelining, forwarding, hazard handling, prediction, etc. A novel high-level functional control fault model is introduced, which has the capability of covering a broad class of gate-level faults. For the functional testing of data-path, bitwise pseudo-exhaustive test method is used. A novel method for measuring the high-level fault coverage is proposed. As an added value of the method, an efficient approach for identifying low-level redundant faults is described. Experimental results demonstrate high fault coverage achieved for MiniMIPS processor without using any information about gate-level implementation details.

Multi-Processor Systems-on-Chip (MPSoCs) have been a clear new trend in processor-based systems design. General purpose MPSoC designers have turned to the Network-on-Chip (NoC) interconnect model to surpass the limitations imposed by traditional bus- or crossbar-based interconnection. This technology is also a promising solution for safety-critical industries where, primarily due to power and weight constraints, there is an increasing need in embedded systems for implementing multiple functionalities upon a single shared computing platform. This paper proposes a QoSinNoC framework, which is based on a set of quality of service (QoS) aware NoC architectures along with the analysis methodology including selected relevant metrics that enable an efficient trade-off between guarantees and overheads in mixed-criticality application scenarios. QoSinNoC architectures overcome the notion of strictly divided regions by allowing non-critical communication pass through the critical region, providing they do not utilize common router resources. This work aims to facilitate the usage of NoC technology by safety-critical industries such as avionics.

Handling faults in computing systems is often expensive in terms of power, area and financial costs. In domains requiring high reliability in harsh environments, like the space domain, special highly reliable components are used, which may adversely impact the processing performance. In this paper, we propose the STROBES algorithm for fault handling in a multi-node embedded system which can be composed of standard commercial off-the-shelf components. In particular, it does not require underlying synchronization, but relies on embedded system's properties to derive bounds for communication and processing times. The algorithm can handle asynchronous behavior between the nodes up to user-defined bounds, in addition to a fault in the state or fail-stop failure of a single node. Theoretical analysis shows that this is sufficient for extended operating times. Experimental data show the efficient behavior of the STROBES algorithm for practical application with different state and time bounds.

The probability that a particular device is operational for a given duration, or reliability, is a dependability attribute and key metric for systems in critical applications. For example, systems for long-term autonomous exploration missions have to be operational during their complete mission. Other critical applications like banking, medical automotive or aerospace face similar reliability requirements that are only met by dependable systems. Traditional dependable systems, compared to their non-dependable counterparts, have three key issues: They are more expensive, consume more power, and provide less performance.

The effectiveness of Assertion-Based Verification (ABV) depends on the quality of assertions. Assertions can be manually or automatically generated. In both cases assertion generation is error prone and needs high expertise. Moreover, the number of generated assertions is generally too large. Thus, assertion qualification is necessary to evaluate the quality of generated assertions to assist verification engineers to select only the highest quality assertions for systems' verification. Most of the current works for assertion qualification are based on fault injection analysis, which requires long simulation time. To fill in the gap, this work proposes a new automatic data mining-based approach for assertions already defined for a design, which in contrast to the state-of-the-art can evaluate assertions' quality precisely within a very short simulation time. Experimental results support the benefit of the proposed methodology.

The shrinking feature size in semiconductor technology beyond the sub-micron domain negatively affects the reliability of digital circuits and makes them more susceptible to run-time faults (such as wear-out and aging) and transient faults during systems life time. This motivates investigation of online faults detection approaches, which would react instantaneously at run-time, concurrent with the system operation. Concurrent online checkers have been one of the approaches introduced in the literature for handling run-time faults online in control part of digital systems. An ideal set of checkers provides high fault detection and localization with minimal area overhead. To reach such optimal set, a diverse initial set of checkers are required which provide a trade-off between the above mentioned parameters. This work presents a methodology to generate (1) high-level functional checkers based on abstract design specification, and (2) structural checkers, which are devised from Register Transfer Level (RTL) description of the circuit. The functional checkers are fewer in number with lower area overhead and provide high fault coverage, however they lead to lower fault localization accuracy and cannot cover all the Single Event Upsets (SEUs). On the other hand, structural checkers provide higher localization accuracy and guarantee 100% SEU coverage, but at the price of higher area overhead. The proposed methodology provides the designer with trade-offs between the parameters mentioned above, for further optimization. The proposed methodology has been applied to the control part of routing logic of a NoC router.

Multi-processor system-on-chip (MPSoC) devices are a well known replacement of single-core devices. Some industries, like avionic, are particularly sensitive to the weight and power consumption. Such industries would really take advantage of reducing the number of computers by using MPSoCs. However, the usage of such devices in safety critical domain is currently more than limited. The main issue, which hinders the MPSoC usage in safety critical field, is the presence of on-chip resources shared by the cores. The interconnection itself is the most evident these shared resources. This aspect is an issue as it undermines the safety aspect of the system by providing non functional dependencies, especially from the timing point of view. The certification process is crucial in safety critical field and the system complexity makes the whole certification process harder and even unfeasible. The certification requires to prove that the system exhibits a precise set of guarantees to the safety-critical tasks. While the complexity was an issue for the well known bus-based MPSoCs, it becomes even more critical for the emerging network-on-chip (NoC) interconnection model. The QoSinNoC framework has been created to analyze a set of simple NoC architectures and the related techniques to enable their usage in the scope of mixed criticality. The main contribution of this work is an alternative routing algorithm which allows a better system utilization without any hardware modifications to the NoC architectures considered by QoSinNoC. Furthermore the framework has been upgraded with the power estimation feature which allows a better design space exploration.

We present an outline of the field of Design Understanding and summarize state-of-the-art research in deriving human-understandable knowledge in form of logic properties from an unknown design.

This is an overview paper that motivates and describes performed work done in the European Commission funded research project BASTION, which focuses on two critical problems of modern electronics: the No-Fault-Found (NFF) and CMOS ageing. New defect classes contributing to NFF have been identified, including timing related faults (TRF) at board level and intermittent resistive faults (IRF) at IC level. BASTION has addressed the mechanisms of ageing and developed several techniques to improve the longevity of electronic products. Embedded Instrumentation, monitors, and IEEE 1687 standard for reconfigurable scan networks (RSN) are seen as an important leverage that helped mitigating the impact of the above listed problems by facilitating a low-latency, scalable online system health monitoring and error localization infrastructure as well as integration of all heterogeneous technologies into a homogeneous demonstration platform. This paper helps the reader to get a general overview of the work performed and provides a collection of references to publications where the respective research results are described in detail.

Due to the ongoing miniaturization of silicon technology beyond the sub-micron domain and the trend of integrating ever more components on a single chip, the Network-on-Chip (NoC) paradigm has emerged to address the scalability and performance shortcomings of bus-based interconnects. As the feature size shrinks, the system gets much more susceptible to faults caused by wear-out and environmental effects. Thus, in order to increase the reliability, creates the need for having mechanisms embedded into such a system that could detect and manage the faults in run-time. In this paper, a ground-up approach from fault detection to fault management for such a NoC-based system on chip is proposed that utilizes both local fault management for fast reaction to faults and a global fault management mechanisms for triggering a large-scale reconfiguration of the NoC. Also, detailed description of strategies for fault detection, localization, classification and propagation to a global fault management unit are provided and methods for local fault management are elaborated.

The recent advancements in the implementation technologies have brought to the front a wide spectrum of new defect types and reliability phenomena. The conventional design techniques do not cope with the integration capacity and stringent requirements of today's nanometer technology nodes. Timing-critical paths analysis is one of such tasks. It has applications in gate-level reliability analysis, e.g., Bias Temperature Instability (BTI) induced aging, but also several others. In this paper, we propose a scalable simulation based technique for explicit identification of true timing-critical paths in both combinational and sequential circuits to enable reliability mitigation approaches, like deciding the paths for delay monitor insertion, resizing delay critical gates or applying rejuvenation stimuli. The paper demonstrates an efficient application of the proposed technique to gate-level NBTI-critical paths identification. The experimental results prove feasibility and scalability of the technique.

With the scaling of silicon technology beyond the sub-micron domain, the probability of the system being exposed to different sources of faults increases. Manifestation of new defects during system's run-time, necessitates the need for a mechanism providing cost-effective online fault detection which performs concurrently with the circuit's normal operation and has low area overhead and high fault coverage. Especially crucial is the fault detection latency, as the system's ability to isolate faults and recover from them is highly dependent on the detection time. This paper proposes two heuristics (branch-and-bound and greedy) for minimization of concurrent online checkers. Both algorithms use the concept of dominant checkers, proposed in this work. The method allows generating minimal area checkers satisfying a target fault coverage with the shortest possible fault detection latency. Experimental results demonstrate the area efficiency of the approach compared to other methods.

Routing algorithms play an important role in Network-on-Chip (NoC) based System-on-Chips. Turn model based routing disallows some of the turns in order to avoid deadlock, while providing partial adaptivity. In this paper, all 2D uniform turn models are examined for deadlock freeness and connectivity; 50 deadlock free turn models are extracted that provide full connectivity in the network. An extended adaptivity metric is introduced to classify the turn models; all extracted turn models are compared in terms of adaptivity, robustness and latency. Experimental results identify the most robust turn models and the most efficient ones in terms of latency.

The time-dependent variation caused by Negative Bias Temperature Instability (NBTI) is agreed to be one of the main reliability concerns in integrated circuits implemented with current nanotechnology nodes. NBTI increases the threshold voltage of pMOS transistors: hence, it slows down signal propagation along logic paths between flip-flops. It may cause intermittent faults and, ultimately, permanent functional failures in processor circuits. In this paper, we study an NBTI mitigation approach in processor designs by rejuvenation of pMOS transistors along NBTI-critical paths. The method incorporates hierarchical fast, yet accurate modelling of NBTI-induced delays at transistor, gate and path levels for generation of rejuvenation Assembler programs using an Evolutionary Algorithm. These programs are applied further as an execution overhead to drive those pMOS transistors to the recovery phase, which are the most critical for the NBTI-induced path delay in processors. The experimental results demonstrate efficiency of evolutionary generation and significant reduction of NBTI-induced delays by the rejuvenation stimuli with an execution overhead of 0.1% or less. The proposed approach aims at extending the reliable lifetime of nanoelectronic processors.

CPS, that consist of a cyber part – a computing system – and a physical part – the system in the physical environment – as well as the respective interfaces between those parts, are omnipresent in our daily lives. The application in the physical environment drives the overall requirements that must be respected when designing the computing system. Here, reliability is a core aspect where some of the most pressing design challenges are: monitoring failures throughout the computing system, determining the impact of failures on the application constraints, and ensuring correctness of the computing system with respect to application-driven requirements rooted in the physical environment. This paper provides an overview of techniques discussed in the special session to tackle these challenges throughout the stack of layers of the computing system while tightly coupling the design methodology to the physical requirements.

The susceptibility of on-chip communication links and on-chip routers to faults has guided the research towards focusing on fault-tolerance aspects of 2D and 3D Network-on- Chips (NoCs). In this paper, we propose Logic-Based Distributed Routing for 3D NoCs (LBDR3D), a scalable, re-configurable and fault-tolerant mechanism, which utilizes only two virtual channels for implementing any deadlock-free turn model routing algorithm in partially vertically connected 3D NoCs. Such networks might emerge either due to the limitation of on-chip area for vertical links or due to occurrence of fault because of wear-out. LBDR3D guarantees live-lock freeness as well as connectivity regardless of the location and number of vertical links as long as faults do not disconnect the network. Our method relies on a limited set of bits which describe the topology and routing algorithm, updated using an offline algorithm. Our Experimental results show the comparison of LBDR3D with three previously proposed fault-tolerant mechanisms, Elevator-First, North-East To Z (NETZ) and East-Then-West (ETW). Compared to Elevator-First, our proposed mechanism is more flexible and in terms of packet latency, it performs better or equal under even extreme fault scenarios for vertical links. Furthermore, as long as the topology is supported by the routing algorithm, LBDR3D can tolerate faults on horizontal links in each layer. In contrast to NETZ and ETW, LBDR3D does not rely on the location of vertical links as long as the network is connected.

On behalf of the Organizing and Program Committees, it is our great pleasure to welcome you to the 24th Annual IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC'16, in Tallinn/Estonia. The conference is held in the Radisson Park Inn Meriton Conference & Spa Hotel, just a couple of footsteps away from the beautiful Old Town of the city. VLSI-SoC 2016 is the 24th in a series of international conferences sponsored by the IFIP TC 10 Working Group 10.5, IEEE CEDA and IEEE CASS, which explores the state-of-the-art in the areas that surround Ultra Large Scale Integration (ULSI) and System-on-Chip (SoC) design and test as well as mixed-technology devices.

The rapid increase of embedded systems design complexity has resulted in emergence of design methodologies at higher levels of abstraction such as Electronic System Level (ESL) and Transaction Level Modeling (TLM) with SystemC language as the main instrument. In practice, system architects and system integrators often have access to a library of legacy Register Transfer Level (RTL) IP (Intellectual Property) cores or obtain new ones from IP design houses. To address architectural exploration, early prototyping and simulation performance, such RTL IP cores are manually recreated at more abstract levels, which implies significant and error-prone effort. The current paper proposes an approach for automated abstraction of the computational part of cycle-accurate RTL IP cores to untimed TLM using a novel concept of SystemC-based Loose Models (SCLM). SCLMs provide for an instrument to neglect design model parts irrelevant for particular manipulation step of the abstraction process, thus simplifying the abstraction flow. As a result, the computational complexity of the abstraction process is reduced, thus increasing the overall scalability. The proposed abstraction flow is demonstrated on a set of benchmark designs and the first experimental results prove feasibility of the proposed approach and also show considerable simulation speed-up.

The paper presents a novel approach to high-level fault modeling and test generation for microprocessors using High-Level Decision Diagrams (HLDD). A general frame-work and novel techniques for automated software-based self-test program generation are discussed. On this basis new previously not published test quality improvement capabilities of the approach are high-lighted and explained. Based on the high level fault model defined for HLDDs a novel class of hard-to-test faults, called "unintended actions", is proposed. In addition, the mechanisms for reducing the risk of fault masking is explained. The experimental results show the superiority of the new method by achieving a higher quality of tests with shorter length compared to the previous results.

Accurate prediction of circuit aging is essential to reliable design, in particular for critical applications. Based on intensive HSPICE electrical simulations, we developed a predictive model to compute NBTI-induced path delay degradation at gate-level. The method is based on a static timing analysis that computes path delay under NBTI-induced VTHp (pMOS transistor threshold voltage) degradation. The proposed approach is demonstrated on an industrial ALU circuit design. The obtained results demonstrate a good fitting between the developed model and HSPICE simulations with several orders of magnitude gain in simulation speed.

This paper proposes a framework for automated evaluation of concurrent online checkers. The novelty of the underlying approach lies in its completeness (i.e. ability of formally proving the presence or absence of true misses), minimal fault detection latency and accurate, fully automated evaluation of the fault detection characteristics of the checkers. The methodology consists of creating a pseudo-combinational version of the circuit under test, specifying the environment in terms of valid input stimuli and providing the assertions for generating the checkers, which will thereafter be evaluated by the framework. In this paper, a case-study on the control part (routing and arbitration) of a Network-on-Chip (NoC) router has been carried out. It shows on a realistic application that the framework is capable of accurately and formally evaluating the quality of individual concurrent checkers which constitutes an important task in fault tolerant system design. The case study shows that the proposed approach helps achieving high fault coverage in a single clock-cycle.

The focus of the paper is detection of faults in NoC routers by combining concurrent checkers with embedded on-line test to enable cost-effective trade-offs between area-overhead and test coverage. First, we propose a framework of tools for formally evaluating the quality of the checkers and for optimizing the overhead area with given fault coverage constraints. The stress is in particular on the minimization of the error detection latency, which is a crucial aspect in order to eliminate (or limit) error propagation. Second, the concurrent checkers will be complemented by embedded on-line test packets which are to be applied as a periodic routine during the idle periods in router operation. The framework together with the corresponding methodology has been successfully applied to a realistic case-study of a fault tolerant NoC router design. The case study shows that combining concurrent routers with embedded test allows reducing the area overhead of the checkers from 31--35% down to 1.5--10% without sacrificing the fault coverage.

The paper presents a new algorithm for structural fault collapsing to reduce search space for test generation, speed up fault simulation and make fault diagnosis easier in digital circuits. The proposed method is based on hierarchical topology analysis of the circuit description. First, the gate-level circuit will be converted into a macro-level network of fan-out-free regions each of them represented by a BDD. This conversion procedure represents the first step of fault collapsing, resulting in a compressed BDD model for representing the remaining set of fault sites. The paper presents an algorithm which implements a complementary step for further fault collapsing, and is carried out at the macro level by topological reasoning of equivalence and dominance relations between the nodes of BDDs. The algorithm has linear complexity and is implemented as a scalable fault collapsing procedure. We introduce higher and lower bounds for structural fault collapsing and provide statistics of distribution of fault collapsing results for a broad set of benchmark circuits. Experimental research has demonstrated better results for structural fault collapsing compared with state-of-the-art.

A new method is presented for simulating of transition delay faults (TDF). The main idea of the method is to extend the TDF model, traditionally considered as a class of robustly tested delay faults, to a class of TDFs with extended detection conditions. Three known fault classes of delay fault sensitization are considered: robust, non-robust and functional sensitization of delay faults. Additionally, a new fault class is introduced, called non-robust functionally sensitized delay fault. A novel fault analysis algorithm based on 7-valued algebra is presented, which delivers the fault coverage for all mentioned four types of TDFs.

A new method for logic simulation and fault modeling in combinational circuits with Structurally Synthesized BDDs (SSBDD) is proposed. The new model is constructed by merging different super-graphs (SSBDDs) related to different circuit outputs, which share as much as possible different subgraphs (SSBDDs) representing the circuit. We call this model as Shared SSBDDs (S3BDD) where each node represents a particular signal path (or segment) of the circuit, and as well the representatives of different fault classes related to this path. A lower bound for the size of the S3BDDmodel for a given circuit, a method for synthesis of S3BDDswith the size close to the lower bound, and a fast logic simulation method based on S3BDDs were developed. Experimental research results support the claims about the efficiency of the model.

SystemC has gained wide acceptance in the design of VLSI SoCs. At the same time there exists a large number of legacy IP cores described in VHDL whose reuse and integration into SystemC ecosystem is highly demanded. However, there is a lack of any standard approach in this regard. This paper proposes an open-source framework and methodology to convert RTL VHDL IP cores to cycle-accurate SystemC designs. The SystemC output is emphasized to be human-readable and providing for clear correspondence to the source VHDL code, thus allowing further manual code changes and debug. The described framework has been implemented based on an open-source zamiaCAD platform and has been successfully applied to translate various VHDL benchmark designs.

One of the main reliability concerns in the nanoscale logic is the time-dependent variation caused by Negative Bias Temperature Instability (NBTI). It may increase the switching threshold voltage of pMOS transistors and as a result slow down signal propagation along the paths between flip-flops thus causing functional failures in the circuit. In this paper we propose an approach to identify NBTI-critical paths in nanoscale logic that is based on analyzing combination in different degrees of the three parameters: delay-critical paths, gate input signal probability and the gate fan-out degree along the paths. Further the identified NBTI-critical path can be used e.g. for introduction of aging sensors circuitry, rejuvenation stimuli generation, etc. The proposed approach is demonstrated on an industrial ALU circuit design.

Current paper proposes a Built-In Self-Test (BIST) architecture for targeting the routing infrastructure of mesh-like NoCs from their boundaries. The architecture contains a counter and a Finite State Machine (FSM) implementing the test configurations. Test data is generated and test responses compacted by a dedicated hardware structure requiring very little silicon area. The advantages of this new boundary BIST concept with respect to existing methods is that costly data wrappers in the NoC network are unnecessary, and thus, area and performance penalties are avoided. We have also improved previously developed test configurations. Experiments show that up to two orders of magnitude gains in the speed of testing are achieved using the new method for large NoCs.

The paper discusses the problem of testing multiple faults in combinational circuits. A definition of a test group is introduced for easier handling of fault masking. Test pair, as a known concept for proving correctness of a line in the circuit is regarded as a special case of the test group. A theorem is proved that if the test group will pass then a particular sub-circuit can be regarded as fault free at any possible combination of stuck-at-faults (SAF) in the circuit. Unlike the traditional approaches, we do not target the faults as test objectives. The goal is to verify the correctness of a part of the circuit. The whole test sequence is presented as a set of test groups where each group has the goal to identify the correctness of a selected part of a circuit.

A new method of test generation based on the concept of partial test groups to prove the correctness of a combinational circuit is proposed. Stuck-at-faults (SAFs) of any multiplicity are assumed to be present in the circuit and we do not need to enumerate them. Unlike the known approaches, we do not target faults as test objectives. The goal is to verify by each test group the correctness of a selected part of the circuit. In case of passing of all the test groups, the circuit is proven fault-free. In case when not all test groups will pass, fault diagnosis by a sequential process of extending the fault-free core is possible.

DIAMOND project is set to cut development costs for Europe's nanoelectronics industry by simplifying error diagnosis and correction in systems. The project reaches beyond current state-of-the-art by taking an integrated approach to localization and correction of different kinds of errors at various levels. In particular, DIAMOND has a focus on automated design error debug, soft error analysis and post-silicon in situ debug fields. The aim is to provide a holistic, systematic methodology and an integrated environment for diagnosis and correction of different types of errors. The DIAMOND consortium includes universities from Estonia, Sweden, Germany and Austria as well as large companies like IBM, Ericsson and two SMEs TransEDA and Testonica Lab. Here, we summarize the main achievements of the project so far.

Verification is increasingly becoming the bottleneck in designing digital systems. In fact, most of the verification cycle is not spent on detecting the occurrences of errors but on debugging, consisting of locating and correcting the errors. However, automated design-error debug, especially at the system-level, has received far less attention than error detection. Current paper presents an automated approach to correcting system-level designs. We propose dynamic-slicing and location-ranking-based method for accurately pinpointing the error locations combined with a dedicated set of mutation operators for automatically proposing corrections to the errors. In order to validate the approach, experiments on the Siemens benchmark set have been carried out. The experiments show that the proposed method is able to correct three times more errors compared to the state-of-the-art mutation-based correction methods while examining fewer mutants.

As of today, RTL still remains the primary abstraction level for VLSI SoC design entry and state-of-the-art design flows need to cope with designs of enormous size, and thus, to scale well. This paper presents an open-source framework zamiaCAD based on a scalable model that includes both, a comprehensive elaboration front-end for RTL design and design processing back-end flows. The persistence and scalability are guaranteed by a custom-designed and highly optimized object database. As an HDL-centric framework it follows the concept of non-intrusiveness. In this paper, we discuss in detail the concepts of design elaboration into the scalable design model and present an evaluation of the model for static analysis as one of the back-end applications. Experimental results on very large designs show that zamiaCAD compares favorable to other frameworks with respect to the scalability aspects.

The paper proposes a novel method for probabilistic equivalence checking of digital systems. The method is based on representing the high-level decision diagrams as the model of digital systems by the sets of characteristic polynomials. It is shown that this representation is canonical, i.e. the sets of polynomials for equivalent diagrams are the same up to the names of the variables. However, computing the full set of polynomials is unfeasible for large diagrams as it demands checking all assignments to the control variables. In order to cope with this problem we have developed a polynomial algorithm for probabilistic equivalence checking.

We propose a hierarchical approach for physical defect diagnosis in combinational or full scan-path digital circuits represented as module networks. As modules we may consider arbitrary subcircuits or library components (e.g. complex gates) of digital circuits. Both, cause-effect and effect-cause approaches are exploited intermittently. The higher level fault diagnosis is carried out in two phases. In the first phase, faulty modules are located by cause-effect analysis using high-level faulty module dictionary. The size of the dictionary depends linearly on the number of modules in the circuit. In the second phase, the set of suspected faulty modules is pruned by effect-cause indirect defect reasoning. At the lower level, the physical defects are directly located in suspected faulty modules. The proposed approach to fault diagnosis helps to cope with the growing complexities of digital circuits. The experimental results show high diagnostic resolution of the proposed approach.

The paper proposes a new hierarchical untestable stuck-at fault identification method for non-scan sequential circuits containing feedback loops. The method is based on deriving, minimizing and solving test path activation constraints for modules embedded into Register-Transfer Level (RTL) designs. First, an RTL test pattern generator is applied in order to extract the set of all possible test path activation constraints for a module under test. Then, the constraints are minimized and a constraint-driven deterministic test pattern generator is run providing hierarchical test generation and untestability proof in sequential circuits. We show by experiments that the tool is capable of quickly proving a large number of untestable faults obtaining high fault efficiency. As a side effect, our study shows that traditional bottom-up test generation based on symbolic test environment generation at RTL is too optimistic due to the fact that propagation constraints are ignored.

In this paper, a new very fast fault simulation method to handle the X-fault model is proposed. The method is based on a two-phase procedure. In the first phase, a parallel exact critical path fault tracing is used to determine all the detected stuck-at faults in the circuit, and in the second phase a postprocess is launched which will determine the detectability of X-faults.

The paper introduces a novel constraint-based automated test pattern generator for Register-Transfer Level (RTL) designs. The tool combines test path constraint activation with a constraint solver. First, a deterministic algorithm that extracts constraints for activating test paths at RTL is applied. Subsequently, a constraint solving package ECLiPSe is used for assembling the tests. Experiments on ITC99 and HLSynth92/95 benchmarks show that the proposed deterministic method offers short run times. In particular, it provides increased fault coverage for hard-to-test designs with respect to earlier, semiformal, approaches.

Logic simulation is a critical component of the design tool flow in modern hardware development efforts. In this paper a new algorithm for parallel logic simulation is proposed based on a new model of Structurally Synthesized Multiple Input BDDs (SSMIBDD). The SSMIBDDs allow further model size reduction and therefore higher speed of logic simulation than its predecessor SSBDD model. The paper presents a method of SSMIBDD synthesis from the given gate network and the main principles of parallel logic simulation with SSMIBDDs. Experimental data demonstrate in average 2.9 times improvement in the speed of logic simulation because of the reduced number of nodes in SSMIBDDs. Similarly to the SSBDDs, the new model preserves structural information about the circuit, which is needed for processing of faults. The reduced complexity of SSMIBDDs leads to the more powerful fault collapsing and as the result to more efficient fault simulation and fault injection to evaluate the dependability of fault tolerant circuits.

The paper presents a new structural fault-independent fault collapsing method for test generation based on the topology analysis of the circuit, which has linear complexity. Fault collapsing is carried out by superposition of binary decision diagrams (BDD) for logic gates, which is used for constructing structurally synthesized BDDs (SSBDD). A new class of SSBDDs with multiple inputs (SSMIBDD) is proposed to reduce the size of collapsed fault sets. Experimental data show that the fault collapsing by the proposed method is more efficient than other strucural fault collapsing methods with comparative time cost are.

The concept of fault model free diagnosis is combined with cause-effect analysis in digital systems represented as networks of functional blocks. We consider the diagnosis as a task to locate a faulty block in the network by using concise block level topological fault dictionaries. The dictionary does not need fault simulation and represents only the connectivity of blocks to observable checkpoints. We define the distance between the entries (codewords) in the dictionary, and make use of these distances to match the observed test responses to the entries of the dictionary. A measure is proposed for evaluating the block-level diagnosability of a given network which can be used for improving the diagnostic resolution. Experimental results provide the data which characterize the proposed measure and show the efficiency of using topological fault dictionaries.

A new improved method for calculation of fault coverage with parallel fault backtracing in combinational circuits is proposed. The method is based on structurally synthesized BDDs (SSBDD) which represent gate-level circuits at higher, macro level where macros represent subnetworks of gates. A topological analysis is carried out to generate an efficient optimized model for backtracing of faults to minimize the repeated calculations because of the reconvergent fanouts. The algorithm is equivalent to exact critical path tracing, however, processing the backtrace in parallel for a group of test patterns. Because of the parallelism, higher abstraction level modeling, and optimization of the topological model, the speed of fault simulation was considerably increased. Compared to the state-of-the-art commercial fault simulators the gain in speed was several times.

Similar to test pattern generation, the problem of identifying untestable faults in sequential synchronous circuits remains unsolved. The previously published works in untestability identification operate at the logic-level and, thus, they do not scale with the increasing complexity of modern designs. Current paper proposes applying model-checking for detecting untestable stuck-at faults at the register-transfer level. In particular, we present a method of generating PSL language assertions for proving untestable register stuck-on faults. Experiments show that the faults identified by the method form in fact a large subset of all the untested stuck-at faults. An additional application of the method is in high-level test synthesis, where testability of sequential designs can be improved simultaneously with minimization of the circuit area. Furthermore, identification of untestable gate-level faults from RT-level can contribute to avoiding over testing and to reducing yield loss.

Current paper proposes a new hierarchical approach to defect-oriented testing of CMOS circuits. The method is based on critical area extraction for identifying the possible shorted pairs of nets on the basis of the chip layout information, combined with logic-level test pattern generation. The novel contributions of the paper are a new bridging fault simulator and a test pattern generator, which are able to handle defects creating feedbacks into the circuit. As a preprocessing step, a combined stuck-at test set from two different test pattern generators implementing alternative strategies (pseudorandom and deterministic) were created. Nevertheless, many short defects were not covered by this extended stuck-at approach. Analyses carried out in this paper show that the stuck-at tests are not covering up to 4% of the shorts (both testable and untestable). The test coverage (fault efficiency) can be increased by the new generator by up to 0.4% in comparison to full stuck-at test. Layout analysis for a set of benchmarks has been performed. The experiments indicate how the number of bridging faults of non-zero probability is dependent on the circuit size.

The paper proposes a novel method for PSL language assertions simulation-based checking. The method uses a system representation model called High-level decision diagrams (HLDD). Previous works have shown that HLDDs are an efficient model for simulation and convenient for diagnosis and debug. The presented approach proposes a temporal extension for the existing HLDD model aimed at supporting temporal properties expressed in PSL. Other contributions of the paper are methodology for direct conversion of PSL properties to HLDD and HLDD-based simulator modification for assertions checking support. Experimental results show the feasibility and efficiency of the proposed approach.

Similar to sequential test pattern generation, the problem of identifying untestable faults in sequential circuits remains unsolved. Most of the previous works in untestability identification operate at the logic-level and, thus, the methods do not scale. Current paper points out a new class of sequentially untestable faults, called register input logic stuck-on faults. We show that it is possible to identify such faults from the register-transfer level (RTL) description of the circuit. Moreover, we prove by experiments that the considered faults form a large subclass of all the untested faults.

This paper presents an optimized fault diagnosing procedure applicable in built-in self-test environments. Instead of the known approach based on a simple bisection of patterns in pseudorandom test sequences, we propose a novel bisection procedure where the diagnostic weight of test patterns is taken into account. Another novelty is the sequential nature of the procedure which allows pruning the search space. Opposite to the classical approach which targets all failing patterns, in the proposed method not all failing patterns are needed to be fixed for diagnosis. This allows to tradeoff the speed of diagnosis with diagnostic resolution. The proposed method is compared with three known fault diagnosis methods: classical binary search, doubling and jumping. Experimental results demonstrate the advantages of the proposed method compared to the previous ones.

The paper proposes a new concept of diagnosing faulty links in network-on-a-chip (NoC) designs. The method is based on functional fault models and it implements packet address driven test configurations. As previous works have shown, such configurations can be applied for achieving near-100 per cent structural fault coverage for the network switches. The main novel contribution of this paper is to extend the use of test configurations for diagnosis purposes and to propose a method for locating faults in the NoC interconnection infrastructure. Additionally, a new concept of functional switch faults, called link faults, is introduced. The approach is well scalable (complexity is square root of the number of switches) and it is capable of unambiguously pinpointing the faulty links inside the switching network.

An efficient method of parallel fault simulation for combinational circuits is proposed. The method is based on structurally synthesized BDDs (SSBDD) which represent gate-level circuits at higher, macro level where macros represent subnetworks of gates. Converting gate-level circuits to the macro-level is accompanied with fault collapsing. A parallel fault analysis algorithm for SSBDDs was developed. For the faults at fanout stems a new full Boolean differential based parallel fault analysis method is proposed. The algorithm is equivalent to exact critical path tracing. Because of the parallelism and higher abstraction level modeling the speed of analysis is considerably increased. Experimental data show that by the new method speed-up measured in several times has been achieved compared to the current state-of-the-art commercial tools and other exact critical path tracing methods.

Over the past few years, network-on-a-chip (NoC) has become increasingly popular as a scalable interconnect infrastructure for IP cores. Simultaneously to developing new design paradigms, testing strategies for such network architectures have to be considered. The previous works on testing NoCs have been mainly based on general purpose design-for-testability (DFT) approaches and there is a lack of test algorithms dedicated to on-chip networks. The main contribution of this paper is a well-scalable external test method, where insertion of wrappers and scan paths will not be required. The paper proposes an external test method for NoC based on functional fault models, which targets single stuck-at faults in the network switches. Furthermore, 100 per cent of delay faults open and shorts between adjacent interconnection lines are covered by the method. The approach allows reaching higher fault coverage in comparison to the recent DFT based solutions

Recently, a number of works have been published on implementing assignment decision diagram models combined with SAT methods to address register-transfer level test pattern generation. Those methods have proven efficient. However, all of them target modules inside the datapath of the circuit. In this paper, we show by experiments that the fault coverage achieved by full datapath tests is often lower than what can be achieved if faults in the control part FSM were additionally considered. We also propose a new type of fault model for targeting faults in FSMs embedded to RTL descriptions. In addition, we present an alternative for traditional assignment decision diagrams, which provides for a more general representation of RTL circuits. We show that our model, called high-level decision diagrams, allows efficient high-level test path activation. According to experiments the proposed approach outperforms state-of-the-art test pattern generation tools

We describe a new e-learning environment and a runtime platform for educational tools on digital system testing and design for testability. This environment is being developed in Tallinn University of Technology and consists of several functional layers. The first one is the hardware component used for illustration of various physical phenomena appearing in defected circuits. In many cases such phenomena are hard to illustrate by software simulation or by any other means, which makes the usage of such a hardware component unavoidable. The second component is a set of university tools covering a large scope of topics in basics of testing, diagnosis, and BIST. The tools represent an efficient alternative to hard-to-learn and expensive commercial CAD systems. The wrapper to these two components is a cross-platform Web interface that represents a server-based solution for using all the available tools and the hardware over Internet. The whole platform is an extendable server-based low-cost solution, which is easy to set-up and use. The learning environment is complemented by laboratory work scenarios and teaching materials that also available in the Web.

Current paper presents new alternatives for accelerating the task of fault simulation for sequential circuits by hardware emulation on FPGA. Fault simulation is an important subtask in test pattern generation and it is frequently used throughout the test generation process. The problems associated to fault emulation for sequential circuits are explained and alternative implementations are discussed. An environment for hardware emulation of fault simulation is presented. It incorporates hardware support for fault dropping. The proposed approach allows simulation speed-up of 40 to 500 times as compared to the state-of-the-art in fault simulation. Average speedup provided by the method is 250 that is about an order of magnitude higher than previously cited in the literature. Based on the experiments, we can conclude that it is beneficial to use emulation when large numbers of test vectors is required.

This work shows a new concept to extend the hierarchical approach of standard-cell circuit design into the area of defect-oriented test pattern generation. For this purpose test patterns to detect shorts for each standard-cell are created separately. A new defect-oriented test generator (DOT) is using these single cell test pattern lists to create test patterns for the complete circuit. Additionally, test patterns for the routing network will be created. This work targets mainly shorts, but also other defects can be treated in a similar way. In order to generate tests only for relevant combinations of shorted nodes, the critical area for both the cells and the routing network is determined separately and the probability for each short is computed. Shorts inside the routing network can show sequential behaviour. The proposed test pattern generator is also able to find tests for such kind of defects. As the effort to test sequential defects can vary from short to short, a new testability analysis is presented. Based on this analysis a redesign of the circuit layout is proposed. This "layout for testability" approach is therefore a defect oriented equivalent for "design for testability" methods.

A method is proposed for combinational deterministic test pattern generation using a uniform functional fault model for combinational circuits. This includes an approach, which allows to find the types of faults that may occur in a real circuit and to determine their probabilities. Additionally, a defect-oriented deterministic test generation tool was developed (DOT), and the experimental data obtained by the tool for ISCAS'85 benchmarks are presented. It was shown that 100% stuck-at fault tests covered only about 80-90% physical defects. The main feature of the new tool is its ability to reach 100% defect efficiency for the given set of defects by proving the redundancy of not detected defects. An interesting conclusion of the experiments is also that up to 25% of the defects cannot be covered by any voltage test approaches.

This paper offers an Internet-based environment for enhancing problem-specific design flows with test pattern generation and fault simulation capabilities. Automatic Test Pattern Generation (ATPG) and fault simulation tools at structural and hierarchical levels available at geographically different places running under the virtual environment using the MOSCITO system are presented. These tools can be used separately, or in multiple applications, for test pattern generation of digital circuits. In order to link different tools together and with commercial design systems, respectively a set of translators was developed. The functionality of the integrated design and test system was verified by several benchmark circuits.

The paper addresses the problem of speeding up functional cycle-based simulation of digital systems. The system is represented as a network of interconnected decision diagrams (DD). Three new innovative simulation algorithms are introduced to implement the idea of simulation execution according to activities of the system variables: forward event-driven algorithm and two versions of back-tracing algorithms. Experiments are presented to show the simulation efficiency improvement offered by those algorithms.

The paper addresses the problem of the cycle-based simulation performance of synchronous digital systems modeled by High-Level Decision Diagrams (DDs). A new class of DD representation, called Register-Oriented DDs (RODD) is introduced. The RODD model appears to be an efficient and compact representation of the system behavior for the high-level cycle simulation. In order to fully exploit the advantages of RODDs a new simulation algorithm, which is a combination of cycle-based forward event-driven and recursive back-tracing techniques is proposed. The characteristics of the simulation algorithms used to efficiently execute the evaluation of the DD network are discussed. Further the experimental results carried out on the real case examples demonstrating the gain in simulation performance of the proposed approach and a comparison of four cycle-based simulation algorithms are presented. Additionally, a comparison with the commercial event-driven and cycle-based HDL simulation tools is included.

A novel approach to testing sequential circuits that uses multi-level decision diagram representations is introduced. The proposed algorithm consists of a combination of scanning and conformity test generation procedures. Structural faults in both, datapath and control part are targeted. High-level simplified and fast symbolic path activation strategy is combined with random local test pattern generation for functional units. The current approach has achieved high fault coverages for known sequential circuit benchmarks in a very short time.

This paper addresses the problem of efficient functional simulation of synchronous digital systems. A technique based on the use of decision diagrams (DD) for representing the functions of a design at RT and behavioural level is introduced. The DD evaluation technique is combined with cycle based simulation mechanism to achieve significant speed up of the simulation execution. Experimental results are provided for demonstrating the efficiency gain of this method in comparison to the event-driven simulation.