100BASE-T2 is a new physical layer specification for IEEE 802.3 LANs operating at 100 Mbit/s ("fast Ethernet"). It enables users of the 10BASE-T Ethernet LAN technology to upgrade their networks from 10 Mbit/s to 100 Mbit/s performance while retaining an existing voice-grade cabling infrastructure. 100BASE-T2 transceivers will operate over two pairs in unshielded twisted-pair cables corresponding to EIA/TIA category 3 (UTP-3), which is the minimum requirement for 10BASE-T. In a four-pair UTP-3 cable, simultaneous operation of two 100BASE-T2 links, or one 100BASE-T2 and one 10BASE-T link, is permitted. Since voice-grade cables exhibit more signal attenuation and significantly higher crosstalk coupling between adjacent pairs than data-grade cables, sophisticated digital signal processing techniques are needed to achieve reliable 100 Mbit/s transmission. The 100BASE-T2 standard defines dual-duplex baseband transmission at a modulation rate of 25 MBaud. During each modulation interval, a four-bit data nibble or Ethernet specific control information is encoded into a pair of quinary signals. These signals are transmitted simultaneously on the two wire pairs in both signalling directions. In the receivers, adaptive digital filters are required for echo and NEXT cancellation, equalization, and interference suppression.

The constrained data access patterns occurring within memory-based packet switches permit the design of application specific SRAM devices that may outperform generic SRAM parts in switch applications. We describe two such devices: one reads and writes a single location in a single 10 ns cycle; the other uses a systolic approach to pipeline accesses in a large array resulting in a 5 ns cycle time.>

An environment for the full-custom design of high-sample-rate digital signal processing (DSP) VLSI circuits is described. An overall design methodology that allows for tradeoffs between algorithms, architecture, and layout is presented. Key CAD tools used in this methodology include architecture mapping, generators, symbolic layout, clock network analysis, and timing simulation. These tools allow designers to move rapidly from specification to layout while keeping a close check on performance parameters such as speed and power dissipation. Two high-speed video chips that were designed using these techniques are described.>

This paper is concerned with the analysis of synchronous, special purpose, multiple-processor systems (including, e.g., systolic arrays). The analysis problem is that of determining the algorithm executed by the system. There has been some prior work in this area, especially by Melhem and Rheinboldt [SIAM J. Comput.,13 (1984), pp. 541–565], who were the first to obtain a general solution. The approach used here is different and apparently simpler. By combining ideas well known in system theory with certain graph-theoretical concepts, a simple procedure for recovering, within a natural equivalence, the iterative algorithm executed by a given special purpose synchronous computing array is obtained. The solution is based on reversing (modulo equivalence) the process by which an iterative algorithm is translated into a logical circuit.

The matrix transform chip (MTC) is designed to perform matrix computations of the form Y=UDV where D is the input data matrix of 16-bit twos complement fixed-point numbers and U, V, are arbitrary coefficient matrices of the same precision. The data matrix D is input to the chip in raster scanned order at a maximum sample rate of 40 MHz, and the output matrix is provided in the same order. On a single chip, the maximum dimension of all matrices must be less than eight, but multiple chips can be cascaded to obtain arbitrary dimensions. The MTC consists of 16 16-bit parallel multipliers/40-bit accumulators, a kilobyte of dual-ported transposition static RAM, and a kilobyte of coefficient static RAM, arranged to interact in a regular iterative architecture. At peak operation, the MTC is capable of performing 0.64 billion fixed-point multiples, 0.64 billion 40-bit accumulates, along with 1.92 billion pseudorandom memory-access operations per second.>

The problem of reducing the amount of interprocessor communication during the distributed factorization of a sparse matrix on a mesh-connected processor network is investigated. Two strategies are evaluated - 1) use of a fragmented distribution of row/columns of the matrix to limit the number of processors to which each row/column segment is transmitted, and 2) use of the elimination tree to permute the matrix so as to internalize as much of the communication as possible. Empirical evaluation of the schemes using matrices derived from circuit simulation shows significant reduction in the amount of communication for a 64 processor mesh.

Some recent results are summarized concerning a class of algorithms known as regular iterative algorithms, particularly with respect to their implementations on processor arrays. Regular iterative algorithms contain all algorithms executed by systolic arrays as a proper subclass and are therefore of considerable importance in real-time signal processing applications. Some general concepts concerning the design of parallel architectures are introduced, and the importance of devising special techniques that utilize any available structure in the algorithm is highlighted. A generic description of the existing methodologies for the systematic design of systolic arrays is given. Using some simple examples, the limitations of these methods are shown. A formal methodology is proposed that overcomes the difficulties in the existing procedures.>

Regular mesh-connected arrays are shown to be isomorphic to a class of so-called regular iterative algorithms. For a wide variety of problems it is shown how to obtain appropriate iterative algorithms and then how to translate these algorithms into arrays in a systematic fashion. Several "systolic" arrays presented in the literature are shown to be specific cases of the variety of architectures that can be derived by the techniques presented here. These include arrays for Fourier Transform, Matrix Multiplication, and Sorting.

An algorithm is presented for the design of systolic arrays that implement single-input single-output time-invariant digital filters. The algorithm is then specialized to the case where the realized array consists only of orthogonal rotational modules and delay elements interconnected in such a manner as to render the circuit pipelineable.