The fast growing mobile market has led to a demand for low power ICs, in order to extend battery life and keep a phone from literally burning a hole in the user's pocket. The microprocessor and high-end System on a Chip field both have a demand for faster ICs. But this is not enough. Mobile devices want to be faster, and high-end devices want to be cooler, if possible. Designers have to be able to tradeoff these conflicting goals to produce products fast enough and cool enough (in both senses of that word) for the marketplace. DFT and test engineers have to deal with this new environment. They have to be able to determine if a particular part hits its speed goals. They have to be able to handle the problems arising from large amounts of switching. For low power parts they have to make sure that scan and BIST do not draw more power than the part can handle, and work around circuitry that turns off parts of the design not in use. Test EDA suppliers have to figure out ways of making their tools work for both high speed and low power designs, and how to help their customers make these nearly impossible tradeoffs. This panel explores these problems and their impact on EDA tools. Three test experts from the design world will answer questions on how they deal with the problems of low power and high speed designs posed by the moderator. Then two panelists from the test EDA sector will suggest how their tools can help — or admit that their tools need more work in that area. Then the discussion will be opened to the audience to allow them to give their solutions to these problems or to pose still tougher problems for us to solve.

We describe methods to use PLL-based transition test in support of chip bring-up. We used it to diagnose slow paths for performance improvement. During bring-up, often the issues of setup, design, scan patterns, and silicon slow paths are mixed together, making diagnosis more difficult. We discuss techniques used to understand and resolve these issues, and show examples of the benefit of transition test over functional and system test.

Delay test is crucial for finding slow paths and slow ICs, both during bringup and during speed binning. Path delay test has traditionally been considered to be superior in finding slow paths. This paper describes our experiments indicating that this is not always the case. For the UltraSPARC T2 microprocessor series we found that transition delay test often ran slower, was more effective in finding the root cause of the slow path, and correlated well with functional diags also used for speed binning. Transition test does a better job finding delay issues related to the impact of simultaneous switching and coupling noise on chip speed. We used transition test to measure the impact on chip timing of voltage, temperature, and we also used it to confirm the results of improving slow paths.

How can we justify system level DFT? We must show that it has a positive return on investment (ROI). Existing test ROI models are manufacturing centric, do not account for the disaggregation of the product realization process, and are often focused on a specific DFT method. We propose a new, top-down, hierarchical ROI model, which starts with potential benefits and can handle entire systems more effectively than current models.

This paper raises the issue of why test engineers often do not act in ways which test economics says are optimal. The new field of behavioral economics explains why people often do not act in their economic self interest, and the authors propose that some of the same principles, applied to testing, can explain some of the behavior of test engineers. The authors use several examples to illustrate these principles, and for each describe the underlying economic and behavioral economic principles behind them, and give recommendations for decision makers

No trouble found (NTF) parts are the bane of the test engineer's existence, since it is difficult to determine the cause of a fail for a part that won't. A companion paper (S. Davidson, 2005) discusses parts that are NTF after failing in the board or system factory. This paper discusses the issue of parts that fail in the field. We classify field NTFs, describe a method of determining the defect coverage of a component under board and system test, and describe how data mining techniques can be used to assist in explaining the causes of field NTFs

As IC feature sizes shrink, density increases, and the number of gates and thus faults explode, we have managed to keep up by developing new fault models and new test generation approaches to detect these faults. Test data size grows with the size of the longest scan chain. Over the last few years many have proposed a solution in the form of test compression. The purpose of this panel is to compare compression methods

This paper gives a model for understanding no trouble found (NTF) parts, including predictions of how many can be expected at different stages of a product life cycle, an understanding of when NTFs are of concern, and when they are to be expected. We also show how NTF rates can be used as a measure of process health.

While the IEEE P1500 standards working group is on the verge of recommending a standard test interface for non-mergeable cores, a need was felt to adopt a standard methodology to achieve easy test interoperability for non-merged core (RTL, gate level) integration. A task force was formed under the P1500 working group investigating this issue and came up with a recommendation. DFT Disclosure Document (DDD) was the outcome of this exercise. The DDD, targeted to be an IEEE standard recommended practice document, aims at capturing the DFT related experience the core provider would like to share with the integrator to facilitate easy test integration. This paper presents the objective and structure of this document along with some use models from participating companies as well as an example.

This article first of all discusses IC test technology and advocates that similar methodologies could be applied to the area of system test. Topics discussed include: product complexity; fault coverage measurement; fault simulation; fault insertion; stuck-at faults; built-in test; DFT; and system diagnostics.

Work in path delay fault testing and fault simulation has gained importance in the industry since supplementing stuck-at fault coverage with delay fault coverage may result in better defect coverage than that is possible with stuck-at fault coverage alone. Timing related failures must be diagnosed to determine which nodes or paths in the circuit have excessive delays and techniques are needed to simplify the process of attributing the delays to a minimal set of nodes or paths. In this work, we propose a method for determining path delay faults that are tested simultaneously by the same test and do not have separate tests either because of circuit functionality or restrictions imposed by a given test set. We call such faults indistinguishable path delay faults. We further propose a method for identifying scanout nodes in the circuit that reduce the number of indistinguishable faults and improve diagnostic resolution. The method for identifying indistinguishable faults can be used before test application to determine the extent of diagnostic resolution possible for a given test set. It also enables a designer to make the design changes needed for improving diagnostic resolution. This has a large impact on the turnaround time for the diagnosis and debug processes. We perform experiments on the partitions of a picoJava/spl trade/ processor core to show the effectiveness of the proposed method. Results show that it requires only a reasonable amount of time for identifying indistinguishable faults and that the proposed methods are practical for deployment in an industrial environment.

Research has shown that single stuck-at fault (SSF) N-detect test sets are effective for detecting defects not modeled by the SSF model. Experimental results showed N-detect coverage is a good metric for determining test quality. In this paper, we examine the test quality of pseudo-random Built-in-Self-Test (BIST) patterns by quantifying the relations between their N-detect coverage and test length. We theoretically derive bounds on the minimum test length of pseudo-random patterns required to achieve a given N-detect coverage. For faults with high detectability, the expected test length for N-detection is around N times the expected test length for single detection. However, for faults with low detectability, the expected test length for N-detection can be NlogN times the expected test length for detecting the fault only once; this increases the test length significantly. We also introduce the idea of effective detectability which is important for analyzing the effectiveness of BIST techniques for detecting real defects.

There are many reasons for high level ATPG, but the major one is the need for ATPG to be done at the same level as design. Today a designer has to drop down to gate level to run an ATPG, while verification and most other design activities can be done in RTL. At one time software debugging tools worked at the assembler level, today they work at the level at which people write. Our ATPG tools should do no less.

In IC diagnosis, failure information is used to isolate the defect to a small set of potential locations, then probing techniques are used to find the actual defect site. Our diagnosis problem is a lot more messy. By definition, the NTF (No Trouble Found) IC fails only at board or system test, making the use of standard IC level diagnostic tools impossible. Sun is fabless, so we do not know common failure modes, have no indication of process and yield history, and don't have access to information that might give a clue as to the cause of failure. The result of diagnosis is an IC test that can detect the failing part, or an understanding of the root cause of the failure sufficient to correct the underlying problem. Since there are so many potential causes of NTFs, the best one can do is develop a set of suggestions for resolving them. Some things that seem to work, at least sometimes, are presented.

I/sub DDQ/ testing is a powerful way to improve the quality of low fault coverage tests, and to detect defects that are hard or impossible to detect using traditional voltage testing methods. However, it appears that there is some yield loss associated with I/sub DDQ/ testing, where yield loss means that devices passing burn-in and system tests fail I/sub DDQ/ test. This paper gives reasons why such yield loss is inevitable, and must be considered when making a decision whether or not to use I/sub DDQ/ testing. We also present some evidence backing up this speculation, and a brief economic model to help in making I/sub DDQ/ testing decisions.

Microcode compaction is an essential tool for the compilation of high-level language microprograms into microinstructions with parallel microoperations. The purpose of the research reported in this paper is to compare four microcode compaction methods reported in the literature: first-come first-served, critical path, branch and bound, and list scheduling. In order to do this a complete, machine independent method of representing the microoperations of real machines had to be developed; and the compaction algorithms had to be recast to use this representation. The compaction algorithms were then implemented and tested on microcode produced by a compiler for a high-level microprogramming language. The results of these experiments were that for all cases examined the first-come first-served and list scheduling algorithms produced microcode compacted into a minimal number of microinstructions in time that was a polynomial function of order two of the number of input microoperations.