In this work we propose a multi-modal architecture for analyzing soccer scenes from tactical camera footage, with a focus on three core tasks: ball trajectory inference, ball state classification, and ball possessor identification. To this end, our solution integrates three distinct input modalities (player trajectories, player types and image crops of individual players) into a unified framework that processes spatial and temporal dynamics using a cascade of sociotemporal transformer blocks. Unlike prior methods, which rely heavily on accurate ball tracking or handcrafted heuristics, our approach infers the ball trajectory without direct access to its past or future positions, and robustly identifies the ball state and ball possessor under noisy or occluded conditions from real top league matches. We also introduce CropDrop, a modality-specific masking pre-training strategy that prevents over-reliance on image features and encourages the model to rely on cross-modal patterns during pre-training. We show the effectiveness of our approach on a large-scale dataset providing substantial improvements over state-of-the-art baselines in all tasks. Our results highlight the benefits of combining structured and visual cues in a transformer-based architecture, and the importance of realistic masking strategies in multi-modal learning.

Multi-agent trajectory modeling has primarily focused on forecasting future states, often overlooking broader tasks like trajectory completion, which are crucial for real-world applications such as correcting tracking data. Existing methods also generally predict agents’ states without offering any state-wise measure of uncertainty. Moreover, popular multi-modal sampling methods lack any error probability estimates for each generated scene under the same prior observations, making it difficult to rank the predictions during inference time. We introduce U2Diff, a unified diffusion model designed to handle trajectory completion while providing state-wise uncertainty estimates jointly. This uncertainty estimation is achieved by augmenting the simple denoising loss with the negative log-likelihood of the predicted noise and propagating latent space uncertainty to the real state space. Additionally, we incorporate a Rank Neural Network in post-processing to enable error probability estimation for each generated mode, demonstrating a strong correlation with the error relative to ground truth. Our method outperforms the state-of-the-art solutions in trajectory completion and forecasting across four challenging sports datasets (NBA, Basketball-U, Football-U, Soccer-U), highlighting the effectiveness of uncertainty and error probability estimation.

Mycelium, the vegetative structure of fungi, exhibits complex electrical signaling patterns when stimulated that resemble neural-like activity, which can be leveraged for bio-inspired computing and sensing applications. To replicate this activity, a 100x100 grid-based circuit has been designed capable of spiking behavior and adaptable configuration thanks to memristive technology aligned with fabricated devices, mimicking the dynamics seen in mycelial networks. Simulations have been carried out to demonstrate that the memristive grid successfully replicates key aspects of mycelium’s electrical activity recorded from experimental setups, including response to environmental stimuli, spiking signal propagation, and eradication.

This work in progress innovative practice paper intends to report on the outline and the ongoing progress of the EU-project GreenChips-EDU, which has been started in October 2023, and intends to fundamentally redesign educational microelectronics programs especially but not limited to students and professionals. One of the major goals is the design of a new microelectronics master program to which six European universities are contributing. The contents of this program will be substantially enhanced with green electronics contents innovative teaching methods. Other work will be done in the field of a new MBA program, self-standing modules for professionals, and a new microelectronics bachelor designed by one university of applied sciences.

Motion prediction in soccer involves capturing complex dynamics from player and ball interactions. We present FootBots, an encoder-decoder transformer-based architecture addressing motion prediction and conditioned motion prediction through equivariance properties. FootBots captures temporal and social dynamics using set attention blocks and multi-attention block decoder. Our evaluation utilizes two datasets: a real soccer dataset and a tailored synthetic one. Insights from the synthetic dataset highlight the effectiveness of FootBots’ social attention mechanism and the significance of conditioned motion prediction. Empirical results on real soccer data demonstrate that FootBots outperforms baselines in motion prediction and excels in conditioned tasks, such as predicting the players based on the ball position, predicting the offensive (defensive) team based on the ball and the defensive (offensive) team, and predicting the ball position based on all players. Our evaluation connects quantitative and qualitative findings. https://youtu.be/9kaEkfzG3L8

In the era of high-performance computing, the integration of Cellular Automata (CA) principles into low-power hardware is a challenging but intriguing endeavor. At the same time, memristors have gained attention due to their potential in in-memory neuromorphic computing. As such, the concept of Wave Cellular Automata (WCA) is presented a novel computing paradigm that leverages CA principles and memristive devices for in-memory computing. However, memristive devices are subject to variability effects, which can impact their performance and, in the case of WCAs, the generation of oscillations crucial for computation. This paper explores the variability tolerance analysis of WCA both in CBRAM device level, but also in its oscillatory behavior. The analysis reveals that WCA operation remains robust even in the presence of variability, with the impact on oscillation amplitude being minor. All in all, proper circuit design and element selection play a significant role in mitigating the effects of variability.

A swarm of miniature robots comprises mini-robots collaborating to achieve common goals, inspired by the collective behavior of insects. This concept mimics decentralized cooperation, enabling complex task accomplishment across various fields such as healthcare, exploration, and rescue missions. Mini-robots operate in confined spaces and time frames with minimal energy, requiring efficient path planning to prevent collisions within their group and surroundings. Integrating ultra-low-power electronics in these robots is essential. Memristors, renowned for their low power consumption, simplicity, and high integration density, hold significant promise. This paper proposes an integrated collision avoidance memristive circuit with neuromorphic behavior for miniature robots. This circuit not only enhances swarm efficiency but also lays the groundwork for fully analog mini-robots.

The resistive switching (RS) technology has many promising applications, but the inherent variability of RS devices has been an important obstacle for the progress towards mass production. Nonidealities of device switching performance have been widely modeled so far, and device degradation has been addressed through testing for fault diagnosis. However, online soft-error “prognosis” concerning both the progressive degradation and transition faults, has been given little consideration. In this direction, we present preliminary results towards the development of prognostics and system health management (PHM) techniques for resistive memory (ReRAM) applications. We propose addressing soft errors through a rich in context scheme used to encode binary information in form of resistance. In out simulations we assumed a ReRAM driver with multi-level READ capability and developed an enhanced progressive feedback-WRITE scheme to ensure not only successful WRITE and reliable READ operations, but also to permit the early online prognosis of potential device failure. Preliminary system-level simulation results validate the expected functionality and represent a reasonable approach towards the design of robust ReRAM controllers.

One of the most prominent examples of a complex system in nature is the nervous system, which exhibits oscil-lation phenomena across its structures, from single neurons to sophisticated neural networks. Memristors have been utilized in the past decade as a promising technology for building neuro-morphic systems due to their intrinsic neuromorphic properties. In this paper, we introduce a novel Memristor-based Oscillator (MBO) circuit design that implements both artificial neurons and artificial synapses in the same MBO-based medium, addressing scalability issues. The circuit design is transistor-free and simple, allowing high integration density. We utilize passive unipolar memristor devices based on the JART memristor model to design MBO neurons, which have been shown to reproduce bio-plausible spiking and bursting activities. Moreover, the MBO circuit is also realized as an artificial synapse incorporating synapse and axon mechanisms. Finally, the MBO neurons are modeled as Parkinson-related neuron types and their direct bidirectional coupling demonstrates that MBO neurons are effective in driving spiking activity in non-externally stimulated MBO neurons. This qualifies them for implementation in brain-inspired networks, providing low-cost Neurological-disease-related emulators.

The threshold switching effect is critical in memristor devices for a range of applications, from crossbar design reliability to simulating neuromorphic features using artificial neural networks. The rich inherit dynamics of a metallic conductive filament (CF) formation are thought to be linked to this characteristic. Simulating these dynamics is necessary to develop an accurate memristor model. In this work we present a compact memristor model that utilizes the drift, diffusion and thermo-diffusion effects. These three effects are taken into consideration to derive the switching behavior of a memristor. The resistance of a memristor is calculated based on the evolution of a truncated cone shaped filament. The objective of this model is to achieve a realistic integration of switching mechanisms of the memristor device, while minimizing the overhead on computing resources and being compatible with circuit design tools. The model incorporates the effect of thermo-diffusion on the switching pattern, providing a different perception of the ionic transport processes, which enable the unipolar switching. SPICE simulation results provide an exact match with experimental results of Metal-Insulator-Metal (MIM) memristive devices of Ag/Si2/SiO2.07/Pt nanoparticles (NPs) configuration.

The beneficial role of noise in the performance of Hf-based memristors has been experimentally studied. The addition of an external gaussian noise to the bias circuitry positively impacts the memristors characteristics by increasing the OFF/ON resistances ratio. The known stochastic resonance effect has been observed, when changing the standard deviation of the noise. The influence of the additive noise on the memristor current-voltage characteristic and on the set and reset related parameters are also presented.

The intrinsic behavioral variability in resistive switching devices (also known as "memristors" or "ReRAM devices") can be a reliability limiting factor or an opportunity for applications where randomness of resistance switching is essential, such as hardware security and stochastic computing. The realistic assessment of ReRAM-based circuits & systems towards practical exploitation requires variability-aware ReRAM modeling. In this context, here we present a versatile, circuit-level implementation strategy to incorporate cycle-to-cycle (C2C) variability to the ReRAM model parameters in SPICE simulations. We evaluated the proposed approach with threshold-based models of a voltage-controlled bipolar ReRAM device and managed to reproduce the main features observed in experimental curves for different pulsed voltage inputs. With key upgrades, compared to previous approaches found in the literature, our strategy enables the enhancement of any ReRAM device model towards the exploration of new ways to make the most of the C2C ReRAM variability, and to test the robustness of any designed circuits & systems against ReRAM variability.

Resistive switching devices -memristors -present a tunable, incremental switching behavior. Tuning their state accurately, repeatedly and in a wide range, makes memristors well-suited for multi-level (ML) resistive memory cells and analog computing applications. In this brief, the tuning approach based on a memristor-resistor voltage divider (VD) is validated here experimentally using commercial memristors from Knowm Inc. and a custom circuit. Rapid and controllable multi-state SET tuning is shown with an appreciable range of different resistance values obtained as a function of the amplitude of the applied voltage pulse. The efficiency of the VD is finally compared against an adaptive pulse-based tuning protocol, in terms of circuit overhead, tuning precision, tuning time, and energy consumption, qualifying as a simple hardware solution for fast, reliable, and energy-efficient ML resistance tuning.

Nonlinear circuits may be interconnected and organized in networks to couple their dynamics and achieve synchronization, a process that is commonly observed in nature. Recent works have shown that memristors may be used as coupling elements in synchronization applications. However, these devices may suffer from low endurance and thus switching faults. Hence, evaluating redundancy and adaptive properties against possible device failures is important. In this direction, we study the performance of a network of chaotic circuits that are coupled using memristors organized in a crossbar geometry. This topology is analyzed in terms of robustness while assuming the existence of defective coupling devices. Our simulation results, based on a physics-based model of bipolar memristor, demonstrate the adaptive behavior of the crossbar architecture and show evidence of different network topologies whose performance outperforms that of the fully functional crossbar.

Since CMOS technology approaches its physical limits, the spotlight of computing technologies and architectures shifts to unconventional computing approaches. In this area, novel computing systems, inspired by natural and mostly nonelectronic approaches, provide also new ways of performing a wide range of computations, from simple logic gates to solving computationally hard problems. Reaction-diffusion processes constitute an information processing method, occurs in nature and are capable of massive parallel and low-power computing, such as chemical computing through Belousov-Zhabotinsky reaction. In this paper, inspired by these chemical processes and based on the wave-propagation information processing taking place in the reaction-diffusion media, the novel characteristics of the nanoelectronic element memristor are utilized to design innovative circuits of electronic excitable medium to perform both classical (Boolean) calculations and to model neuromorphic computations in the same Memristor-RLC (M-RLC) reconfigurable network.

Stochastic Resonance (SR) is a nonlinear system specific phenomenon, which was demonstrated to lead to system unexpected (counter-intuitive) performance improvements under certain noise conditions. Memristor, on the other hand, is a fundamentally nonlinear circuit element, thus susceptible to benefit from SR, which recently came in the spotlight of the emerging technologies potential candidates. However, at this time, the variability exhibited by manufactured memristor devices within the same array constitutes the main hurdle in the road towards the commercialisation of memristor-based memories and/or computing units. Thus, in this paper, memristor SR effects are explored, assuming various memristor models, and SR-based memristance range enhancement, tolerant to device-to-device variability, is demonstrated. Our experiments reveal that SR can induce significant RMAX/RMINratio increase under up to 60% variability, getting as high as 3.4× for 29 dBm noise power.

With the advent of the slowdown in DRAM capacitor scaling [1] and the increased reliability problems of traditional 6T SRAM memories [2], industry and academia have looked for alternative memory cells. Among those, gain-cells have attracted significant attention due to their smaller size (compared to SRAM) and non-destructive read operation (compared to DRAM) as well as considerable low power and reasonable robustness. This paper first summarizes the available evidences of SRAM and eDRAM in commercial and test chips. Then, it analyzes the performance, reliability and scaling of eDRAM gain-cells in 10 and 7 nm FinFET technology; as well as above and below VT(i.e. sub-threshold).

The technology of Resistive Switching (RS) devices (memristors) is continuously maturing on its way towards viable commercial establishment. So far, the change of resistance has been identified as a function of the applied pulse characteristics, such as amplitude and duration. However, parameter variability holds back any universal approach based on these two magnitudes, making also difficult even the qualitative comparison between different RS material compounds. On the contrary, there is a relevant magnitude which is much less affected by device variability; the energy. In this direction, we doubt anyone so far has ever wondered “what is the quantitative effect of the injected energy on the device state?” Interestingly, a first step was made recently towards the definition of performance parameters for this emerging device technology, using as fundamental parameter the energy. In this work, we further elaborate on such ideas, proving experimentally that the “resistance change per energy unit” $( dR/ dE )$ can be considered a significant magnitude in analog operation of bipolar memristors, being a key performance parameter worth of timely disclosure.

Cellular Automata (CA) is a nature-inspired and widespread computational model which is based on the collective and emergent parallel computing capability of units (cells) locally interconnected in an abstract brain-like structure. Each such unit, referred as CA cell, performs simplistic computations/processes. However, a network of such identical cells can exhibit nonlinear behavior and be used to model highly complex physical phenomena and processes and to solve problems that are highly complicated for conventional computers. Brain activity has always been considered one of the most complex physical processes and its modeling is of utter importance. This work combines the CA parallel computing capability with the nonlinear dynamics of the memristor, aiming to model brain activity during the epileptic seizures caused by the spreading of pathological dynamics from focal to healthy brain regions. A CA-based confrontation extended to include long-range interactions, combined with the recent notion of memristive electronics, is thus proposed as a modern and promising parallel approach to modeling of such complex physical phenomena. Simulation results show the efficiency of the proposed design and the appropriate reproduction of the spreading of an epileptic seizure.

Unconventional computing has been studied intensively, even after the appearance of CMOS technology. Currently, it has returned to the spotlight because CMOS is about to reach its physical limits, given that the constant demand for more computational power requires for novel unconventional computing solutions. In this area, the oscillatory internal motion mechanism of slime mould, namelyPhysarum Polycephalum, could serve as an alternative concept for the design and development of electronic circuits that exploit the memristive dynamics and simple LC contours to deliver solutions for computationally hard to be solved problems. In this direction, this work presents how bio-inspired memristive LC oscillators with a coupling capacitor can be synchronized to perform the functionalities of a biological neuron, also able to execute more complex computations, aiming to model biological neural systems much more advanced than the neuron-less slime mould biological organism. This work proposes a connection between the function mechanism of a simple biological organism and that of complex biological systems, made in a plausible and sufficient manner, towards unconventional computation with memristors.

This paper presents a fully digital implementation of a memristor hardware (HW) simulator, as the core of an emulator, based on a behavioral model of voltage-controlled threshold-type bipolar memristors. Compared to other analog solutions, the proposed digital design is compact, easily reconfigurable, demonstrates very good matching with the mathematical model on which it is based, and complies with all the required features for memristor emulators. We validated its functionality using Altera Quartus II and ModelSim tools targeting low-cost yet powerful field-programmable gate array families. We tested its suitability for complex memristive circuits as well as its synapse functioning in artificial neural networks, implementing examples of associative memory and unsupervised learning of spatiotemporal correlations in parallel input streams using a simplified spike-timing-dependent plasticity. We provide the full circuit schematics of all our digital circuit designs and comment on the required HW resources and their scaling trends, thus presenting a design framework for applications based on our HW simulator.

Finding a product in the fashion world can be a daunting task. Everyday, e-commerce sites are updating with thousands of images and their associated metadata (textual information), deepening the problem, akin to finding a needle in a haystack. In this paper, we leverage both the images and textual metadata and propose a joint multi-modal embedding that maps both the text and images into a common latent space. Distances in the latent space correspond to similarity between products, allowing us to effectively perform retrieval in this latent space, which is both efficient and accurate. We train this embedding using large-scale real world e-commerce data by both minimizing the similarity between related products and using auxiliary classification networks to that encourage the embedding to have semantic meaning. We compare against existing approaches and show significant improvements in retrieval tasks on a large-scale e-commerce dataset. We also provide an analysis of the different metadata.

Memristors are emerging devices known by their nonvolability, compatibility with CMOS processes and high density in circuits density in circuits mostly owing to the crossbar nanoarchitecture. One of their most notable applications is in the memory system field. Despite their promising characteristics and the advancements in this emerging technology, variability and reliability are still principal issues for memristors. For these reasons, exploring techniques that check the integrity of circuits is of primary importance. Therefore, this paper proposes a method to perform an on-line test capable to detect a single failure inside the memory crossbar array.

Resistive switching Random Access Memories (RRAM) are being considered as a promising alternative for conventional memories mainly due to their high speed, scalability, CMOS compatibility, Non-Volatile behavior (NVM), and consequent orientation to low power consumption. Advances in the RRAM technology as well as enhancement of the control of the cells are opening the use of these devices for multi-valued logic. But the cycle-to-cycle variability and the still reduced endurance are becoming serious limitations. This paper analyzes the impact of both mechanisms on 1T1R cells and suggests potential adaptive mechanisms to enlarge its lifetime.

We propose a new superpixel algorithm based on exploiting the boundary information of an image, as objects in images can generally be described by their boundaries. Our proposed approach initially estimates the boundaries and uses them to place superpixel seeds in the areas in which they are more dense. Afterwards, we minimize an energy function in order to expand the seeds into full superpixels. In addition to standard terms such as color consistency and compactness, we propose using the geodesic distance which concentrates small superpixels in regions of the image with more information, while letting larger superpixels cover more homogeneous regions. By both improving the initialization using the boundaries and coherency of the superpixels with geodesic distances, we are able to maintain the coherency of the image structure with fewer superpixels than other approaches. We show the resulting algorithm to yield smaller Variation of Information metrics in seven different datasets while maintaining Undersegmentation Error values similar to the state-of-the-art methods.

Bio-medical wearable devices restricted to their small-capacity embedded-battery require energy-efficiency of the highest order. However, minimum-energy point (MEP) at sub-threshold voltages is unattainable with SRAM memory, which fails to hold below 0.3V because of its vanishing noise margins. This paper examines minimum-energy operation of 2T and 3T1D e-DRAM gain cells as an alternative to SRAM at 32nm technology node with different design points: up-sizing transistors, using high-Vth transistors, read/write wordline assists and temperature. First, the e-DRAM cells are evaluated without considering any process variations. The design-space is explored by creating a kriging meta-model to reduce the number of simulations. Finally, a full-factorial statistical analysis of e-DRAM cells is performed in presence of threshold voltage variations. The effect on mean MEP is also reported.

In this paper, we analyze the suitability of implementing embedded DRAM (eDRAM) cells on FinFET technology compared to classical planar MOSFETs. The results show a significant improvement in overall cell performance for multi-gate devices. While pFinFET-based memories showed better cell behavior and variability robustness, mixed n/pFinFET cells had the highest working frequency and a negligible impact on degradation. Finally, we show that a multiple fin-height strategy can be used to reduce the layout area of the eDRAM cells (>10%).

We propose a robust and efficient method to estimate the pose of a camera with respect to complex 3D textured models of the environment that can potentially contain more than 100; 000 points. To tackle this problem we follow a top down approach where we combine high-level deep network classifiers with low level geometric approaches to come up with a solution that is fast, robust and accurate. Given an input image, we initially use a pre-trained deep network to compute a rough estimation of the camera pose. This initial estimate constrains the number of 3D model points that can be seen from the camera viewpoint. We then establish 3D-to-2D correspondences between these potentially visible points of the model and the 2D detected image features. Accurate pose estimation is finally obtained from the 2D-to-3D correspondences using a novel PnP algorithm that rejects outliers without the need to use a RANSAC strategy, and which is between 10 and 100 times faster than other methods that use it. Two real experiments dealing with very large and complex 3D models demonstrate the effectiveness of the approach.

Nanoscale circuits are subject to a wide range of new limiting phenomena making essential to investigate new design strategies at the circuit and architecture level to improve its performance and reliability. Proactive reconfiguration is an emerging technique oriented to extend the system lifetime of memories affected by aging. In this brief, we present a new approach for static random access memory (SRAM) design that extends the cache lifetime when considering process variation and aging in the memory cells using an adaptive strategy. To track the aging in the SRAM cells we propose an on-chip monitoring technique. Our results show the technique as a feasible way to extend the cache lifetime up to 5X.

With the growing importance of parametric (process and environmental) variations in advanced technologies, it has become a serious challenge to design reliable, fast and low-power embedded memories. Adopting a variation-aware design paradigm requires a holistic perspective of memory-wide metrics such as yield, power and performance. However, accurate estimation of such metrics is largely dependent on circuit implementation styles, technology parameters and architecture-level specifics. In this paper, we propose a fully automated tool - INFORMER - that helps high-level designers estimate memory reliability metrics rapidly and accurately. The tool relies on accurate circuit-level simulations of failure mechanisms such as soft-errors and parametric failures. The statistics obtained can then help couple low-level metrics with higher-level design choices. A new technique for rapid estimation of low-probability failure events is also proposed. We present three use-cases of our prototype tool to demonstrate its diverse capabilities in autonomously guiding large SRAM based robust memory designs.

Negative bias temperature instability (NBTI) is a major cause of concern for chip designers because of its inherent ability to drastically reduce silicon reliability over the lifetime of the processor. Coupled with statistical variations of process parameters, it can potentially render systems dysfunctional in certain scenarios. Data caches suffer the most from such phenomenon because of the unbalanced duty cycle ratio of SRAM cells and maximum intrinsic susceptibility to process variations. In this paper, we propose a novel NBTI-aware technique, invert-Read-Modify-Write (iRMW) that can improve the functional yield of the data cache significantly over its lifetime. Using architecture-level benchmarks, we first analyse the impact of activity factor and workload variation on NBTI-induced failures in data caches. iRMW is then used as a means to balance the duty cycle by alternating between recovery and stress cycle upon successive read accesses to the cache line. The highly transient nature of the data stored in L1 data cache aides this process of recovery upon using iRMW. A unique feature of iRMW is its intelligent use of low-leakage & NBTI-tolerant embedded-DRAM cells as an alternative to SRAM-cells for storing important state information. Our experiments conducted using SPEC2006 and PhysicsBench workloads show that on-average the cache failure probability can be reduced by 22%, 33% and 36% after two, four and eight years of processor usage respectively. In addition to being extremely power-frugal, use of eDRAM reduces total area footprint of iRMW tremendously.

Scaling of device dimensions toward nano-scale regime has made it essential to innovate novel design techniques for improving the circuit robustness. This work proposes an implementation of adaptive proactive reconfiguration methodology that can first monitor process variability and BTI aging among 6T SRAM memory cells and then apply a recovery mechanism to extend the SRAM lifetime. Our proposed technique can extend the memory lifetime between 2X to 4.5X times with a silicon area overhead of around 10% for the monitoring units, in a 1kB 6T SRAM memory chip.

In view of device scaling issues, embedded DRAM (eDRAM) technology is being considered as a strong alternative to conventional SRAM for use in on-chip memories. Memory cells designed using eDRAM technology in addition to being logic-compatible, are variation tolerant and immune to noise present at low supply voltages. However, two major causes of concern are the data retention capability which is worsened by parameter variations leading to frequent data refreshes (resulting in large dynamic power overhead) and the transient reduction of stored charge increasing soft-error (SE) susceptibility. In this paper, we present a novel variation-tolerant 4T-DRAM cell whose power consumption is 20.4% lower when compared to a similar sized eDRAM cell. The retention time on-average is improved by 2.04X while incurring a delay overhead of 3% on the read-access time. Most importantly, using a soft-error (SE) rate analysis tool, we have confirmed that the cell sensitivity to SEs is reduced by 56% on-average in a natural working environment.

Due to increased leakage currents and variability, classical bulk technology is reaching its scaling limits and some alternatives must be found. FinFETs are one of those alternatives. Through their 3D structure, they achieve better channel control which is the key to scalability. However, some sources of variability still remain. The impact of this technology shift on SRAM and DRAM memories is analyzed in this work.

Process variations and device aging have a significant impact on the reliability and performance of nano scale integrated circuits. Proactive reconfiguration is an emerging technique to extend the lifetime of embedded SRAM memories. This work introduces a novel version that modifies and enhances the advantages of this method by considering the process variability impact on the memory components. Our results show between 30% and 45% SRAM lifetime increases over the existing proactive reconfiguration technique and between 1.7X and ~10X improvement over the non-proactive reconfiguration.

In silicon bulk CMOS technology the variability of the device parameters is a key drawback that may be a limiting factor for further miniaturizing nodes. New nanoscale beyond-CMOS devices are being studied such as carbon nanotubes (CNTs). The goal of this paper is to evaluate the parameter variability in Carbon Nanotube Field Effect Transistors (CNFETs) and its potential capability to be a promising alternative to Si-CMOS technology. The impact of the carbon nanotube diameter variations as well as the presence of metallic carbon nanotubes in the transistor are analyzed (device level). This variability model is used to make a comparison between Si-MOSFET and CNFET Static Random Access Memory (SRAM) 6T cells (circuit level).

Memory circuits are playing a key role in complex multicore systems with both data and instructions storage and mailbox communication functions. There is a general concern that conventional SRAM cell based on the 6T structure could exhibit serious limitations in future CMOS technologies due to the instability caused by transistor mismatching as well as for leakage consumption reasons. For L1 data caches the new cell 3T1D DRAM is considered a potential candidate to substitute 6T SRAMs. We first evaluate the impact of the positive bias temperature instability, PBTI, on the access and retention time of the 3T1D memory cell implemented with 45 nm technology. Then, we consider all sources of variations and the effect of the degradation caused by the aging of the device on the yield at system level.

In this paper, we propose a dynamically tunable fine-grain body biasing mechanism to reduce standby leakage power in first level data-caches under process variations. Accessed physical arrays are forward body biased (FBB) to improve latency while idle (unaccessed) arrays are reverse body biased (RBB) for reducing standby leakage power. The bias voltage to be applied is computed at design time and updated at run-time to counter the negative effects of process variations. This ensures that under all scenarios, the cache will consume the lowest leakage power for the target access latency computed at design-time. A sensor-like hardware mechanism measures the variation in latency and leakage at run-time and this measurement is used to update the bias voltage. The backbone of the hardware used for measurement is a three-transistor one-diode(3T1D)DRAM cell embedded into a regular cache array. By measuring the access and retention time of the 3T1D cell, we show that it is possible to classify cache arrays based on run-time latency/leakage profiles. Our technique reduces leakage energy consumption and access latency of the cache on an average by 20% & 18% respectively. Finally we show that our technique will improve parametric yield by a maximum of 38% for worst-case scenario.

The TRAMS (Terascale Reliable Adaptive MEMORY Systems) project addresses in an evolutionary way the ultimate CMOS scaling technologies and paves the way for revolutionary, most promising beyond-CMOS technologies. In this abstract we show the significant variability levels of future 18 and 13nm device bulk-CMOS technologies as well as its dramatic effect on the yield of memory cells, and what kind of circuit solution would be required to maintain the current yield level. Later, we discuss the impact of errors at the system level, and different approaches at system level to adapt the heterogeneous systems to user's requirements.

Environmental conditions are changing all the time along the chip as a consequence of its own activity, provoking deviations on propagation time in digital circuits. In future technologies, the increment of devices sensitivity to environmental fluctuations yields to a wider range of possible time deviations, being for example, in an NOT gate designed in a 16 nm technology 1.6 times larger than for a 45 nm version. But this ratio is different for every circuit cause it depends on its fundamental structure and characteristics. In this paper the tendency of timing parameters deviations due to environmental factors fluctuation and how these deviations have deeper impact on more complex structures are analyzed. It is shown that the internal structure of the logic gates cause a mismatch between logic circuits and in future technologies it will be enlarged.

With every process generation, the problem of variability in physical parameters and environmental conditions poses a great challenge to the design of fast and reliable circuits. Propagation delays which decide circuit performance are likely to suffer the most from this phenomena. While Statistical static timing analysis (SSTA) is used extensively for this purpose, it does not account for dynamic conditions during operation. In this paper, we present a multivariate regression based technique that computes the propagation delay of circuits subject to manufacturing process variations in the presence of temporal variations like temperature. It can be used to predict the dynamic behavior of circuits under changing operating conditions. The median error between the proposed model and circuit-level simulations is below 5%. With this model, we ran a study of the effect of temperature on access time delays for 500 cache samples. The study was run in 0.557 seconds, compared to the 20h and 4min of the SPICE simulation achieving a speedup of over 1×105. As a case study, we show that the access times of caches can vary as much as 2.03× at high temperatures in future technologies under process variations.

Estimation of static and dynamic energy of caches is critical for high-performance low-power designs. Commercial CAD tools performing energy estimation statically are not aware of the changing operating and environmental conditions which makes the problem of energy estimation more dynamic in nature. It is worsened by process induced variations of low level parameters like threshold voltage and channel length. In this paper we present MODEST, a proposal for estimating the static and dynamic energy of caches taking into account spatial variations of physical parameters, temporal changes of supply voltage and environmental factors like temperature. It can be used to estimate the energy of different blocks of a cache based on a combination empirical data and analytical equations. The observed maximum and median error between MODEST and HSPICE energy-estimates for 22,500 samples is around 7.8% and 0.5% respectively. As a case study, using MODEST, we propose a two step iterative optimization procedure involving Dual-V th assignment and standby supply voltage minimization for reclaiming energy-constrained caches. The observed energy reduction is around 50.8% for the most-leaky Cache. A speed-up of 750X over conventional hard-coded implementation for such optimizations is achieved.

Layout regularity is introduced progressively by integrated circuit manufacturers to reduce the increasing systematic process variations in the deep sub-micron era. In this paper we focus on a scenario where layout regularity must be pushed to the limit to deal with severe systematic process variations in future technology nodes. With this objective, we propose and evaluate a new regular layout style called Via-Configurable Transistor Array (VCTA) that maximizes regularity at device and interconnect levels. In order to assess VCTA maximum layout regularity tradeoffs, we implement 32-bit adders in the 90 nm technology node for VCTA and compare them with implementations that make use of standard cells. For this purpose we study the impact of photolithography proximity and coma effects on channel length variations, and the impact of shallow trench isolation mechanical stress on threshold voltage variations. We demonstrate that both variations, that are important sources of energy and delay circuit variability, are minimized through VCTA regularity.

The power dissipated by the devices of an integrated circuit can be considered a signature of the circuit's performance. Without disturbing the circuit operation, this power consumption can be monitored by temperature measurements on the silicon surface. In this paper, the frequency response of a RF LNA is observed by measuring spectral components of the sensed temperature. Results prove that temperature can be used to debug and observe figures of merit of analog blocks in a RFIC. Experimental measurements have been done in a 0.25 mum CMOS process. Laser probing techniques have been used as temperature sensors; specifically, a thermoreflectometer and a Michaelson interferometer.

The talk will reconsider the role of the test in new emerging device circuits for CMOS Terascale and further technologies where a high level of redundancy will be present. As far as we are getting close to ultimate CMOS and ulterior new emerging nano-devices technologies the indication made by J. von Neumann in 1950 that errors had to be viewed not as an extraneous accident but as an essential part of the process under consideration caused by natural phenomena is becoming a real fact. It is well accepted that at the same time electronic technology is going into the deep nanoscale the device reliability decreases rapidly. For such future technologies internal electromagnetic coupling or just thermal noise as well as permanent manufacturing defects will cause a loss of reliability and introduce an inherent error probabilistic factor to every component of the system. These deviations motivate new design paradigms. Many of these deviations will be transient in nature, at the same time current computer architecture approaches are reaching their practical limits. In order to build reliable electronics it will be necessary to include fault and defect tolerant schemes through the introduction of massive redundancy. Within this change of scenario, in comparison to conventional deterministic logic circuits these emerging technologies have to face new design and test strategies in order to give support to this probabilistic behavior logic.

Testing today of a several hundred million transistor system-on-chip with analog, RF blocks, many processor cores and tens of memories is a huge task. What the test technology be like in year 2020 with hundreds of billions of transistors on a single chip? Can we get there with tweaks to today's technology? While the exact nature of the circuit styles, architectural innovations and product innovations in year 2020 are highly speculative at this point, we examine the impact of likely design and process technology trends on testing methods

In this paper, an efficient technique to evaluate temporal correlation and transition activity at high level in DSP systems is presented. The method is based on the spectral distribution of signals and has the advantage to require information well known by designer, simple and easy to apply even for complex circuits. With only the knowledge of the input signal spectrum and the transfer function from the input to the circuit nodes allows an efficient estimation of the correlation coefficients. A model for computing transition activity in terms only of spectral distribution is also developed. The spectral analysis gives new criteria to obtain power optimization. Experimental results validating the method are also included in this paper

Measuring techniques of the die surface temperature in integrated circuits are reported as very appropriate for failure analysis, for thermal characterization, and for testing modern devices. The paper is arranged as a survey of techniques oriented towards measuring the temperature dynamics of the circuit surface and presenting and discussing both the merits and drawbacks of each technique with regard to the accuracy, reliability and efficiency of the measurements. Two methods are presented in detail: laser probing methods, based on interferometry and thermoreflectance, and embedded CMOS circuit sensors. For these techniques, the physical principles, the state of the art in figures of merit and some application examples are presented

In this paper we introduce a design methodology that allows the system/circuit designer to build reliable systems out of unreliable nano-scale components. The central point of our approach is a generic (parametrical) architectural template. Configurable nanostructures for reliable nano electronics (CONAN), which embeds support for reliability at various levels of abstractions. Some of the main reliability sources are regular and decentralized structures based on simple basic computation cells designed to be robust against disturbances and noise, fault tolerance based on hardware, time and information redundancy applied at the basic cell level as well as at higher levels, self diagnosis assisted by the dynamic reconfiguration of basic computation cells and interconnect rerouting. Within the CONAN template, both technology dependent and independent models co-exists such that the more abstract layers are technology independent while the lower levels can be retargeted to various fabrication technologies. Our proposal is application-oriented and allows the designers to deal with unpredictability, and low reliability, which are unavoidable characteristics of future emerging nano-devices. When combined with the underlying software, the tools supporting the CONAN approach allow the designer to check whether the design constraints are fulfilled before performing a detailed implementation and provides means to trade area, delay, and power consumptions for reliability. As such, this proposal is a call-to-arms to mobilize the efforts of systems designers in order to achieve a systematic design methodology for reliable systems.

Temperature is a physical magnitude that can be used as an observable quantity for IC testing purposes. The authors discuss in this paper the suitability of two temperature measuring strategies applicable to standard CMOS integrated circuits: a laser interferometer and a differential fully CMOS built-in temperature sensor.

By measuring the temperature at some points of an IC during a test procedure, defects can be detected (fault testing). With a simple processing of the measured temperature waveform, the distance between the temperature monitoring point and the activated defect can be derived. This paper presents four temperature measuring strategies to determine this distance for diagnosis purposes.

Temperature can be used as a test observable: some failures when activated produce an increase in local power dissipation, changing the surface thermal map of the IC, being detectable with built-in thermal sensors. In this work, both the feasibility of this testing technique and the generation of the specific test pattern are discussed.

A new testing alternative based on thermal wave propagation is proposed. Some failures, when activated, produce an increase in local power dissipation at various points. A thermal wave is generated by this increase and can be used as a test observable. In this paper, both the thermal wave and the heat sources that appear for a set of faults are characterised and a built-in sensing strategy based on differential considerations is analysed.

I/sub DDQ//I/sub SSQ/ testing has been a popular topic for production testing of CMOS integrated circuits (ICs). Although this type of testing shows promise for board and system level testing, there exist limitations in the implementation of such testing. This paper proposes integrating boundary scan and I/sub DDQ/ testing at the integrated circuit level so that I/sub DDQ/ testing can be accomplished at the board and system level for improved system reliability.

The properties of Gate Oxide Short defects (GOS) in CMOS circuits are investigated identifying the most relevant parameters that determine the behavior of a defective device. Electrical models of the defect are developed and compared with experimentation. Depending upon location and transistor type, GOSs are resistive, diode, parasitic MOSFET or parasitic BJT. We also investigate the necessary conditions to detect a GOS at the circuit level, providing the bases for an efficient ATPG approach.

I/sub DDQ/ testing is a powerful strategy for detecting defects that do not alter the logic behavior of CMOS ICs. Such a technique is very effective especially in the detection of bridging defects although some opens can be also detected. However, an important set of open and parametric defects escape quiescent power supply current testing because they prevent current elevation. Extending the consumption current testing time, from the static period to the dynamic one (i.e. considering the transient current), defects not covered with I/sub DDQ/ can be detected. Simulations using an on-chip sensor show that this technique can reach a high coverage for defects preventing current and also for those raising the static power consumption.

An exhaustive classification of bridging faults between pairs of logic level circuit nodes and an I/sub DDQ/ testability analysis scheme for these faults are presented in this paper. The case of feedback bridging faults producing oscillations is considered in detail. The testability of such faults is verified through a set of experiments with specially implemented ASIC's.>

The behavior of an MOS transistor with an open in the polygate path (floating transistor gate defect) is investigated and its effect on the quiescent power supply current I/sub DDQ/ is studied. The possible detection of this defect by current testing is explored in fully complementary CMOS circuits. The behavior of a transistor with its floating gate is modeled using the coupling capacitances in the floating gate and the charge in the transistor gate. The poly-bulk and metal-poly capacitances are found to be two significant parameters in determining the degree of conduction on the affected transistor. The induced voltage in the floating gate and the quiescent current are estimated by analytical expressions. The model is compared with SPICE 2 simulations. Good agreement is observed between the simple analytical expressions, simulations and experimental measures performed on defective circuits. In addition, it is shown that the floating gate transistor can be modeled as a weakly conductive stuck-on transistor or as a stuck-open transistor depending on the values of the parameters characterizing the defect.>

The continuous reduction of the device size in integrated circuits and the increase in the switching rate cause parasitic capacitances between conducting layers to become dominant and cause logic errors in the circuits. Therefore, capacitive couplings can be considered as potential logic faults. Classical fault models do not cover this class of faults. This paper presents a logic level characterization and fault model for crosstalk faults. The authors also show how a fault list of such faults can be generated from the layout data, and give an automatic test pattern generation procedure for them.>

This paper details the architecture and design of a VLSI CMOS retina dedicated to very fast pattern recognition. The implementation of the recognition algorithms into silicon are detailed. The performances of the ixj pixel retina are evaluated for various input pattern sizes. A 64*32 pixel integrated circuit design is presented which performs a pattern recognition and localisation in less than 100 mu s. The application considered is character recognition.>