This paper proposes a dual loop low-dropout regulator (LDO) for heavy load current (I$_{\mathbf {L}}$). The proposed LDO features a fast load transient response and wide output capacitor (C$_{\mathbf {O}}$) range. The proposed dynamic negative feedback loop (DNFL) enhances the transient response by reducing the undershoot and widening the bandwidth. The transient response is improved further by the proposed dynamic G$_{\mathbf {m}}$boosting error amplifier. The C$_{\mathbf {O}}$range gets wider thanks to the proposed DNFL, which introduces an additional zero in the feedback loop. The zero secures stability in a wide C$_{\mathbf {O}}$range. The prototype of the proposed LDO is fabricated in a 0.5-$\mu $m CMOS process. The input voltage (V$_{\mathbf {IN}}$) ranges from 2.7 to 4.2 V, while the output voltage (V$_{\mathbf {O}}$) ranges from 2.4 to 4.0 V. The maximum I$_{\mathbf {L}}$is 2 A. The prototype provides enough phase margin across a C$_{\mathbf {O}}$range from 0 to$1~\mu $F. The measured results show a 68-mV undershoot with a load current of 2.5 A/$1~\mu $s on a 0-$\mu $F C$_{\mathbf {O}}$capacitor. When the C$_{\mathbf {O}}$is$1~\mu $F under the same conditions, the proposed LDO features an undershoot of 13 mV. The proposed LDO achieves the best FoM among the state-of-the-art LDOs without and with the off-chip C$_{\mathbf {O}}$. In cases where the off-chip C$_{\mathbf {O}}$is not employed, the achieved FoM is 5.228 ps$\cdot V/\mu $m2. When using the off-chip C$_{\mathbf {O}}$, the FoM is 0.624 ps/$\mu $m2.

This paper presents a charge-sharing based customized 8T SRAM in-memory computing (IMC) architecture. In the proposed IMC approach, the multiply-accumulate (MAC) operation of multi-bit activations and weights is supported using the charge sharing between bit-line (BL) parasitic capacitances. The area-efficient customized 8T SRAM macro can achieve robust and voltage-scalable MAC operations due to the charge-domain computation. We also propose a split capacitor structure-based 5/6-bit reconfigurable successive approximation register analog-to-digital converter (SAR-ADC) to reduce the hardware cost of an analog readout circuit while supporting higher precision MAC operations. The proposed reconfigurable SAR-ADC has been exploited to implement layer-by-layer mixed bit-precisions in convolution layer for increasing energy efficiency with negligible accuracy loss. The 256×64 8T SRAM IMC macro has been implemented using 28nm CMOS process technology. The proposed SRAM macro achieves 11. 20-TOPS/W with a maximum clock frequency of 125MHz at 1. 0V. It also supports supply voltage scaling from 0.5V to 1.1V with the energy efficiency ranging from 8.3-TOPS/W to 35.4-TOPS/W within 1 % accuracy loss.

This paper presents 6T SRAM cell-based bit-parallel in-memory computing (IMC) architecture to support various computations with reconfigurable bit-precision. In the proposed technique, bit-line computation is performed with a short WL followed by BL boosting circuits, which can reduce BL computing delays. By per-forming carry-propagation between each near-memory circuit, bit-parallel complex computations are also enabled by iterating operations with low latency. In addition, reconfigurable bit-precision is also supported based on carry-propagation size. Our 128KB in/near memory computing architecture has been implemented using a 28nm CMOS process, and it can achieve 2.25GHz clock frequency at 0.9V with 5.2% of area overhead. The proposed architecture also achieves 0.68, 8.09 TOPS/W for the parallel addition and multiplication, respectively. In addition, the proposed work also supports a wide range of supply voltage, from 0.6V to 1.1V.

Binarized neural network (BNN) is one of the most promising solution for low-cost convolutional neural network acceleration. Since BNN is based on binarized bit-level operations, there exist great opportunities to reduce power-hungry data transfers and complex arithmetic operations. In this paper, we propose a content addressable memory (CAM) based BNN accelerator. By using time-domain signal processing, the huge convolution operations of BNN can be effectively replaced to the CAM search operation. In addition, thanks to fully parallel search of CAM, the parallel convolution operations for non-overlapped filtering window is enabled for high throughput data processing. To verify the effectiveness of the proposed CAM based BNN accelerator, the convolutional layer of LeNet-5 model has been implemented using 65nm CMOS technology. The implementation results show that the proposed BNN accelerator achieves 9.4% and 38.5% of area and energy savings, respectively. The parallel convolution operation of the proposed approach also shows 2.4x improved processing time.

This paper presents an adaptive match-line (ML) discharging scheme for low power and high speed ternary content addressable memory (TCAM). In the proposed TCAM, by employing the gated ML pulldown path and ML boosting scheme, the redundant ML discharging and SL switching are eliminated while improving the search speed. By considering the number of mismatch and ML discharging speed, the ML discharging is adaptively controlled in the proposed TCAM. The simulation results with the 65nm CMOS technology show that the proposed adaptive ML discharging scheme improves up to 19% of sensing delay and saves 81% of ML power compared to the conventional approach. When compared with the state-of-the-art work, the post-layout simulations show 10% improvement of FOM (energy/bit/search).

This paper presents a low area and energy efficient hardware accelerator for the deep convolutional neural networks (CNNs). Based on the multiply-accumulate (MAC) based architecture, three design techniques are proposed to reduce the hardware cost of the convolutional computations. First, to reduce the computational bit-width of convolutions, an adaptive bit-width reduction scheme is proposed based on differential input method. The bit-width reduction approach can reduce the 37 % of operation bit-width with almost ignorable CNN accuracy degradation. Second, it has been found that adapting bi-directional filtering window in CNN accelerator can considerably reduce the energy for data movement with much smaller number of memory accesses. To expedite the bi-directional filtering operations, we also propose a bidirectional first-input-first-output (bi-FIFO). With SRAM bit-cell layout manner, the proposed bi-FIFO facilitates fast data re-distribution with area and energy efficiency. To verify the effectiveness of the proposed techniques, the AlexNet accelerator has been designed. The numerical results show that the proposed adaptive bit-width reduction scheme achieves 25.9% and 47.3% of area and energy savings, respectively. The bi-FIFO based accelerator also achieves 33 % improved processing time.

Accurate yield estimation under parametric variation is one of the most integral parts for robust and nonwasted circuit design. In particular, due to the significant impact of disparity on the high-replication circuit, precise yield estimation is essential in SRAM design. In this paper, we propose an enhanced perturbation vector generation method to improve the accuracy of the yield estimation of the conventional direct SRAM yield computation method, which are access disturb margin (ADM) and write margin (WRM) first, by splitting the concave yield metric space, the estimation error caused by linear approximation can be significantly reduced with minor increase in simulation runtime. In addition, to compensate the inaccuracy of the conventional perturbation vector, a calibration method to reflect the multi-dc condition in SRAM assist operations is also proposed. Numerical results show that 37% improved estimation accuracy and 29% reduced estimation error can be achieved compared to the conventional ADM/WRM in the wide voltage range.

In this paper, we present embedded dynamic random access memory (eDRAM)-based memory customization techniques for low-cost fast Fourier transform (FFT) processor design. The main idea is based on the observation that the FFT processor has regular and predictable memory access patterns, and it can be efficiently exploited for memory customization using eDRAM. The memory customization approaches are applied to both of the pipelined and memory-based FFT architectures. In the pipelined architecture, the read wordline (RWL) coupling write assist and data packing schemes are employed to reduce the redundant RWL and wordline driving, respectively, in columninterleaved memory arrays. The memory address decoder is also simplified with thermometer code by exploiting the sequential access patterns. For the memory-based architecture, the modified cached-memory structure is employed in addition to the techniques used in the pipelined FFT architecture. The hardware implementation results of 2k-point FFT with a 0.11-um CMOS technology show that the proposed eDRAM-based pipelined and cached-memory FFTs achieve 26.8% and 33.2% power savings over the static RAM-based FFT design, respectively.

We tried to build a virtual Yamahoko Parade experiencing system as a digital museum research for Kyoto Gion Festival. We collected route data and acceleration data of Hayashibutai, the performance stage of the Yamahoko float, with a GPS logger and acceleration sensors during the parade. We adopted the data to reproduce the vibration using a vibration platform and integrated vibration, sound, and 3D screen to build an experimental system. The analysis of the reproduced acceleration data and the original acceleration data showed that the virtual experiencing system reproduced the vibration of the Hayashibutai. We also received positive feedbacks from the experts participated in our experiment.

The purpose of this research is to make a quantitative analysis of Iaido (the Japanese art of using the Japanese sword) proficiency with multivariate data analysis. We carried out experiments of motion capture on Kirioroshi (a straight overhead slash) movement of Roppon-me (a sword thrust using two hands) in Iaido. We can analyze the proficiency of an Iaido practitioner by conducting PCA (Principal Components Analysis) and cluster analysis of parameters of body movement. In addition, it is expected that our research will help Iaido practitioners and masters with Iaido training through giving new information on Iaido movements.

The purpose of this research is to make a quantitative analysis of leg movement patterns of expert dancer, which cannot be analyzed with a motion capture system alone, using simultaneous measurement of body motion and biophysical information (EMG: electromyogram). We carried out experiments on traditional Japanese dance, Nihonbuyo. We can analyze leg movements of expert Japanese traditional dancer by calculating a center of gravity in human body and co-contraction of muscles in knee and ankle using biomechanics method. In addition, it is expected that our research will help dancers and researchers on dance through giving new information on dance movements which cannot be analyzed with motion capture alone.

We have proposed a human-scale interaction system (i.e. reactive virtual human system) with haptic sensation. This system is composed of a wire-based haptic interface and an immersive virtual environment (VE). Based on the framework, we realized virtual catch ball that a user can play a virtual human with a feeling of contacting real ball. To make a database of virtual human's natural reaction, we implemented reactive motion capture system that can capture movements with physical reaction in close interpersonal engagements. In this paper, we further show the system's extended function that new motions can reflect on virtual human's behavioral structure by an on-line motion capture. It will be a practical way to produce various motion patterns during playing, and to enforce virtual human's adaptive function.