We present a novel deep-learning method using the ConvMixer network for automatic earthquake location. The proposed ConvMixer network utilizes three-component waveform recordings of single stations for estimating the hypocenter location. The ConvMixer network is a patch-based architecture that combines depthwise and pointwise convolutions to extract the global and local information of the earthquake waveforms. We train and test the proposed method using the Italian seismic dataset (INSTANCE). The ConvMixer network estimates the earthquake hypocenter locations with high accuracy, reaching a mean absolute error (MAE) of 2.71 km for the epicenter distance, and 1.15 km for the depth. In addition, we use the global STanford EArthquake Dataset (STEAD) to further evaluate the performance of the ConvMixer. As a result, the ConvMixer network achieves MAEs of 2.27 km and 1.19 km for the distance and the depth, respectively. The proposed ConvMixer network is compared to the benchmark methods, i.e., ResNet, AlexNet, MobileNet, and Xception, and outperforms all of them.

We propose a novel deep learning method using an attention-based fully convolutional dense network (FCDNet) for automatic earthquake detection. The FCDNet consists of encoder-decoder parts with skip connections, where each encode-decoder block contains a block of densely connected layers to enhance the feature learning capability. The spatial attention mechanism is added within the FCDNet to assign greater attention to useful features and hence improve the accuracy of earthquake detection. The time-frequency representations of three-component seismograms produced by the Stockwell transform are used for better extracting the hidden data features. The attention-based FCDNet extracts the time-frequency features needed for distinguishing the seismic signal from the background noise. We evaluate the performance of the proposed method using a Mediterranean dataset. The attention-based FCDNet is trained using 90% of the Mediterranean dataset and tested using the remaining 10%. Accordingly, the training and testing accuracies are 97.71% and 97.02%, respectively. The intersection over union (IoU), precision, recall, and F1-score of the attention-based FCDNet are 93.80%, 99.72%, 99.55%, and 99.64%, respectively. Moreover, to evaluate the generalization ability of the trained model, we utilize 100,000 seismic waveforms recorded in different seismic regions from the global STanford EArthquake Dataset (STEAD) dataset for testing, which shows robust performance. We also apply the attention-based FCDNet to the Japanese seismic data and compare the performance to the CRED and SCALODEEP methods. The attention-based FCDNet outperforms the benchmark methods and achieves a higher detection accuracy of 99.46%. The attention-based FCDNet is additionally evaluated using one-day continuous seismic data recording a seismic swarm that occurred in the Helike region. As a result, the attention-based FCDNet recognizes 135 earthquakes and raises 15 false alarms with a detection accuracy of 90.06%.

The multiprocessor system on chips (MPSoCs) are considered today the core of most modern systems. Most of the applications of these heterogeneous MPSoCs include critical systems and hence terms of fault tolerance and reliability have become essential. Task replication is a technique to carry out fault tolerance and can help for reducing the schedule length by increasing locality. It introduces an upper and lower bound for the makespan of each schedule while each task is replicated more than once. If a fault occurs during execution, the expected makespan will be some value between the upper bound and the lower bound based on when and where the fault has occurred. In this research a new performance parameter namely the weighted average makespan is introduced. It is calculated as the average of the lower and upper bounds of makespan using the probability of occurrence of each. Two scheduling algorithms are presented for fault tolerant scheduling based on directed acyclic graphs. These algorithms are the list scheduling algorithm and the optimizing of the weighted average makespan based on simulated annealing method. The simulation results show that the techniques can improve the schedule length and increase the system reliability without compromising the performance.

This paper focuses on solving the Boolean Satisfiability (SAT) problem using a parallel implementation of the Ant Colony Optimization (ACO) algorithm for execution on the Graphics Processing Unit (GPU) using NVIDIA CUDA (Compute Unified Device Architecture). We propose a new efficient parallel strategy for the ACO algorithm executed entirely on the CUDA architecture, and perform experiments to compare it with the best sequential version exists implemented on CPU with incomplete approaches. We show how SAT problem can benefit from the GPU solutions, leading to significant improvements in speed-up even though keeping the quality of the solution. Our results shows that the new parallel implementation executes up to 21x faster compared to its sequential counterpart.

This paper presents different multiprocessor implementations of the proportional-integral-derivative (PID) controller using two technologies: 1) field programmable gate array (FPGA)-based multiprocessor system-on-chip (MPSoC); and 2) multicore microcontrollers (MCUs). Techniques to implement a parallelized PID controller, a multi-PID controller, and a self-tuning PID controller are proposed. These techniques are verified using hardware (HW) in the loop (HIL) simulations. Then, the paper presents a detailed case study of an embedded real-time (RT) self-tuning PID controller for a 1-degree-of-freedom (1-DOF) aerodynamical system. This includes controller design, parameters tuning, and implementation using a multiprocessor system. Results proved the effectiveness of the proposed techniques to improve performance and functionality. It is shown that customizing HW and software (SW) within MPSoCs provides higher RT performance. Moreover, using multicore MCUs can reduce design time, implementation time, and cost, while keeping adequate performance. Therefore, it is possible to realize and implement complex RT embedded controllers that employ advanced control algorithms in rapid, effective, and cost-efficient fashion.

A multi-processor system is an integrated circuit containing multiple processor cores that implements most of the functionality of a complex electronic system and some other components like FPGA/ASIC on a single chip. In this paper, we present a novel approach to synthesize multi-core system architectures from Task Precedence Graphs (TPG) models. The front end engine applies efficient algorithm for scheduling and communication contention resolving to obtain the optimal multi-core system architecture in terms of number of processor cores, number of busses, task-to-processor/channel-to-bus mapping, optimal schedule, and hardware-software (HW-SW) partition. The scheduling and mapping algorithms produce the optimality of mapping tasks onto cores. The partitioning technique reduces the overall execution time and number of buses among the cores. The back end engine generates a SystemC simulation model using a well-known commercial tool model generation library. The viability and potential of the proposed algorithms are demonstrated by a case study and extensive experimental results to conclude that the proposed approach is an efficient scheme to obtain the optimality of scheduling, mapping and partitioning with hard and large task graph problems.

In this paper, efficient hardware-software (HW-SW) partitioning technique based on high performance scheduling and mapping algorithms on multiple cores is presented. The scheduling and mapping algorithms produce the optimality of mapping tasks onto cores. The partitioning technique reduces the overall execution time and number of buses among the cores. The viability and potential of the proposed algorithms are demonstrated by extensive experimental results to conclude that the proposed algorithms are efficient scheme to obtain the optimality of scheduling, mapping and partitioning with hard and large task graph problems.