EDBT 2026 Demo / reviewers in the wild / expert
Chris Nyberg
dblp:56/100
· DBLP profile ↗
3ranked-venue papers
2as first author
0since 2021 · last 1995
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Databases, data management, data science and information retrieval · 2 · 2 first-authorSystems, architecture and hardware · 1Software engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Performance modeling and evaluation · 44% High-performance computing · 26% Memory systems · 17% | |
| Databases, data mining, and information retrieval
1 paper |
Query processing and optimization · 100% |
Topics — the 8 heaviest of 10, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Query processing and optimization
sorting |
0.0 | 1 | 1994 | AlphaSort: A RISC Machine Sort · SIGMOD Conference 1994 |
Performance modeling and evaluation
benchmarking |
0.0 | 1 | 1994 | AlphaSort: A RISC Machine Sort · SIGMOD Conference 1994 |
Performance modeling and evaluation › benchmarking › algorithm benchmarking
sort benchmark |
0.0 | 1 | 1994 | AlphaSort: A RISC Machine Sort · SIGMOD Conference 1994 |
Memory systems › cache
cache-aware algorithm design |
0.0 | 1 | 1995 | AlphaSort: A Cache-Sensitive Parallel External Sort · VLDB J. 1995 |
Memory systems
cache |
0.0 | 1 | 1983 | Architecture of a VLSI Instruction Cache for a RISC · ISCA 1983 |
Memory systems › cache › CPU cache
instruction cache |
0.0 | 1 | 1983 | Architecture of a VLSI Instruction Cache for a RISC · ISCA 1983 |
Processor architecture and microarchitecture › instruction fetch
instruction fetch unit |
0.0 | 1 | 1983 | Architecture of a VLSI Instruction Cache for a RISC · ISCA 1983 |
Processor architecture and microarchitecture › instruction set architecture
RISC |
0.0 | 1 | 1983 | Architecture of a VLSI Instruction Cache for a RISC · ISCA 1983 |
Methods — techniques the papers use, named apart from their topics
quicksort · 0.0file striping · 0.0parallel external sorting · 0.0cache-sensitive partitioning · 0.0replacement-selection · 0.0replacement selection · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1995 | AlphaSort: A Cache-Sensitive Parallel External Sort
Chris Nyberg, Tom Barclay, Zarka Cvetanovic, Jim Gray 0001, David B. Lomet |
VLDB J. | 1 |
| 1994 | AlphaSort: A RISC Machine SortabstractA new sort algorithm, called AlphaSort, demonstrates that commodity processors and disks can handle commercial batch workloads. Using Alpha AXP processors, commodity memory, and arrays of SCSI disks, AlphaSort runs the industry-standard sort benchmark in seven seconds. This beats the best published record on a 32-cpu 32-disk Hypercube by 8:1. On another benchmark, AlphaSort sorted more than a gigabyte in a minute.AlphaSort is a cache-sensitive memory-intensive sort algorithm. It uses file striping to get high disk bandwidth. It uses QuickSort to generate runs and uses replacement-selection to merge the runs. It uses shared memory multiprocessors to break the sort into subsort chores.Because startup times are becoming a significant part of the total time, we propose two new benchmarks: (1) Minutesort: how much can you sort in a minute, and (2) DollarSort: how much can you sort for a dollar. Chris Nyberg, Tom Barclay, Zarka Cvetanovic, Jim Gray 0001, David B. Lomet |
SIGMOD Conference | 1 |
| 1983 | Architecture of a VLSI Instruction Cache for a RISCabstractA cache was first used in a commercial computer in 1968,1 and researchers have spent the last 15 years analyzing caches and suggesting improvements. In designing a VLSI instruction cache for a RISC microprocessor we have uncovered four ideas potentially applicable to other VLSI machines. These ideas provide expansible cache memory, increased cache speed, reduced program code size, and decreased manufacturing costs. These improvements blur the habitual distinction between an instruction cache and an instruction fetch unit. David A. Patterson 0001, Phil Garrison, Mark D. Hill, Dimitris Lioupis, Chris Nyberg, Tim Sippel, Korbin S. Van Dyke |
ISCA | 5 |