Demo Data from EDBT 2026 / reviewers in the wild / expert
Jian-Huei Guo
dblp:56/10548
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1998
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Performance modeling and evaluation · 77% Integrated circuit design · 23% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Performance modeling and evaluation
probabilistic performance analysis |
0.0 | 1 | 1998 | Hierarchical Algorithms for Assessing Probabilistic Constraints on System Performance · DAC 1998 |
Integrated circuit design
low-power circuit design |
0.0 | 1 | 1998 | Hierarchical Algorithms for Assessing Probabilistic Constraints on System Performance · DAC 1998 |
Methods — techniques the papers use, named apart from their topics
probabilistic delay modeling · 0.0monte carlo simulation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1998 | Hierarchical Algorithms for Assessing Probabilistic Constraints on System PerformanceabstractWe propose an algorithm for assessing probabilistic performance constraints for systems including components with uncertain delays. We make a case for designing systems based on a probabilistic relaxation of performance constraints, as this has the potential for resulting in lower silicon area and/or power consumption. We consider a concrete example, an MPEG decoder, for which we discuss modeling and assessment of probabilistic throughput constraints. Gustavo de Veciana, Margarida F. Jacome, Jian-Huei Guo |
DAC | 3 |